Datasheet

Page x of xxx
2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)................. 75
2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn..... 75
2.7.5 Absolute Address—@aa:8/@aa:16/@aa:24/@aa:32.............................................. 75
2.7.6 Immediate—#xx:8/#xx:16/#xx:32.......................................................................... 76
2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC) ...................................... 76
2.7.8 Memory Indirect—@@aa:8 ................................................................................... 77
2.7.9 Effective Address Calculation ................................................................................ 78
2.8 Processing States.................................................................................................................. 80
2.9 Usage Note........................................................................................................................... 82
2.9.1 Usage Notes on Bit-wise Operation Instructions.................................................... 82
Section 3 MCU Operating Modes .......................................................................83
3.1 Operating Mode Selection ................................................................................................... 83
3.2 Register Descriptions...........................................................................................................84
3.2.1 Mode Control Register (MDCR) ............................................................................ 84
3.2.2 System Control Register (SYSCR)......................................................................... 85
3.3 Operating Mode Descriptions.............................................................................................. 87
3.3.1 Mode 1.................................................................................................................... 87
3.3.2 Mode 2.................................................................................................................... 87
3.3.3 Mode 3.................................................................................................................... 87
3.3.4 Mode 4.................................................................................................................... 88
3.3.5 Mode 7.................................................................................................................... 88
3.3.6 Pin Functions .......................................................................................................... 89
3.4 Memory Map in Each Operating Mode ............................................................................... 90
Section 4 Exception Handling .............................................................................97
4.1 Exception Handling Types and Priority............................................................................... 97
4.2 Exception Sources and Exception Vector Table.................................................................. 98
4.3 Reset .................................................................................................................................. 100
4.3.1 Reset Exception Handling .................................................................................... 100
4.3.2 Interrupts after Reset............................................................................................. 102
4.3.3 On-Chip Peripheral Functions after Reset Release............................................... 102
4.4 Trace Exception Handling ................................................................................................. 103
4.5 Interrupt Exception Handling ............................................................................................ 104
4.6 Trap Instruction Exception Handling................................................................................. 105
4.7 Illegal Instruction Exception Handling .............................................................................. 106
4.8 Stack Status after Exception Handling............................................................................... 107
4.9 Usage Note......................................................................................................................... 108