Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 144 (20x20) 16-Bit 32 MHz I/O number 96

User's Manual

All information contained in these materials, including products and product

specifications, represents information on the product at the time of publication and is

subject to change by Renesas Electronics Corp. without notice. Please review the

latest information published by Renesas Electronics Corp. through various means,

including the Renesas Electronics Corp. website (http://www.renesas.com).

H8S/2456, H8S/2456R, H8S/2454 Group

User’s Manual: Hardware

ev.

201

Renesas 16-Bit Single-Chip Microcomputer

H8S Family / H8S/2400 Series

H8S/2456 R4F2456

R4S2456

H8S/2456R R4F2456R

R4S2456R

H8S/2454 R4F2454

R4S2454

The revision list summarizes the locations of

revisions and additions. Details should always

be checked by referring to the relevant text.

www.renesas.com

Summary of content (1442 pages)

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User's Manual 16 The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.
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Page ii of xxx
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Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2.
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1.
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How to Use This Manual 1. Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual.
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2. Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. (1) Overall notation In descriptions involving the names of bits and bit fields within this manual, the modules and registers to which the bits belong may be clarified by giving the names in the forms "module name"."register name"."bit name" or "register name"."bit name".
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3. Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below. (1) [Table of Bits] Bit (2) (3) (4) (5) Bit Name − − Initial Value R/W Description 0 0 R R Reserved These bits are always read as 0. 13 to 11 ASID2 to ASID0 All 0 R/W Address Identifier These bits enable or disable the pin function.
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4. Description of Abbreviations The abbreviations used in this manual are listed below.
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Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 1.4 Features.................................................................................................................................. 1 1.1.1 Applications.............................................................................................................. 1 1.1.2 Overview of Specifications.................................................................
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2.8 2.9 2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)................. 75 2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn..... 75 2.7.5 Absolute Address—@aa:8/@aa:16/@aa:24/@aa:32.............................................. 75 2.7.6 Immediate—#xx:8/#xx:16/#xx:32.......................................................................... 76 2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC) ...................................... 76 2.7.
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Section 5 Interrupt Controller ............................................................................109 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Features.............................................................................................................................. 109 Input/Output Pins............................................................................................................... 111 Register Descriptions ...........................................................................
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6.3.6 6.4 6.5 6.6 6.7 Area 0 Burst ROM Interface Control Register (BROMCRH) Area 1 Burst ROM Interface Control Register (BROMCRL) .............................. 169 6.3.7 Bus Control Register (BCR) ................................................................................. 170 6.3.8 Address/Data Multiplexed I/O Control Register (MPXCR) ................................. 172 6.3.9 DRAM Control Register (DRAMCR) .................................................................. 173 6.3.
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6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.7.10 Byte Access Control ............................................................................................. 236 6.7.11 Burst Operation..................................................................................................... 238 6.7.12 Refresh Control..................................................................................................... 244 6.7.13 DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface.....
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6.15.3 External Bus Release Function and CBR Refreshing/Auto Refreshing................ 318 6.15.4 BREQO Output Timing ........................................................................................ 319 6.15.5 Notes on Usage of the Synchronous DRAM ........................................................ 319 Section 7 DMA Controller (DMAC).................................................................321 7.1 7.2 7.3 7.4 7.5 7.6 7.7 Features....................................................
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Section 8 EXDMA Controller (EXDMAC) ......................................................407 8.1 8.2 8.3 8.4 8.5 8.6 Features.............................................................................................................................. 407 Input/Output Pins............................................................................................................... 409 Register Descriptions .................................................................................................
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9.5 9.6 9.7 9.8 Operation ........................................................................................................................... 491 9.5.1 Normal Mode........................................................................................................ 494 9.5.2 Repeat Mode......................................................................................................... 495 9.5.3 Block Transfer Mode ...........................................................................
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10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.3.4 Port 3 Open Drain Control Register (P3ODR) ..................................................... 565 10.3.5 Pin Functions ........................................................................................................ 566 Port 4.................................................................................................................................. 570 10.4.1 Port 4 Register (PORT4)............................................................
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10.11 10.12 10.13 10.14 10.15 10.16 10.10.6 Pin Functions ........................................................................................................ 621 10.10.7 Port B Input Pull-Up MOS States......................................................................... 629 Port C ................................................................................................................................. 630 10.11.1 Port C Data Direction Register (PCDDR) ..................................
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10.16.2 Port H Data Register (PHDR)............................................................................... 677 10.16.3 Port H Register (PORTH)..................................................................................... 677 10.16.4 Port H Open Drain Control Register (PHODR).................................................... 678 10.16.5 Pin Functions ........................................................................................................ 679 10.17 Port J .....................
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11.5 11.6 11.7 11.8 11.9 Interrupt Sources................................................................................................................ 772 DTC Activation.................................................................................................................. 776 DMAC Activation.............................................................................................................. 776 A/D Converter Activation.................................................................
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12.4.7 Inverted Pulse Output ........................................................................................... 818 12.4.8 Pulse Output Triggered by Input Capture ............................................................. 819 12.5 Usage Notes ....................................................................................................................... 820 12.5.1 Module Stop Function Setting .............................................................................. 820 12.5.
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13.8.8 Interrupts in Module Stop State ............................................................................ 846 Section 14 Watchdog Timer (WDT) ................................................................. 847 14.1 Features.............................................................................................................................. 847 14.2 Input/Output Pin ................................................................................................................ 848 14.
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15.5 15.6 15.7 15.8 15.9 15.10 15.4.3 Clock..................................................................................................................... 897 15.4.4 SCI Initialization (Asynchronous Mode).............................................................. 898 15.4.5 Data Transmission (Asynchronous Mode) ........................................................... 899 15.4.6 Serial Data Reception (Asynchronous Mode) ......................................................
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16.3 Register Descriptions ......................................................................................................... 951 16.3.1 Interrupt Flag Register 0 (IFR0) ........................................................................... 952 16.3.2 Interrupt Flag Register 1 (IFR1) ........................................................................... 954 16.3.3 Interrupt Flag Register 2 (IFR2) ........................................................................... 955 16.3.
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16.6 16.7 16.8 16.9 16.10 16.5.6 EP1 Bulk-Out Transfer ....................................................................................... 1004 16.5.7 EP2 Bulk-In Transfer.......................................................................................... 1005 16.5.8 EP3 Interrupt-In Transfer.................................................................................... 1007 Processing of USB Standard Commands and Class/ Vendor Commands........................ 1008 16.6.
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17.4.3 Master Receive Operation .................................................................................. 1040 17.4.4 Slave Transmit Operation ................................................................................... 1043 17.4.5 Slave Receive Operation..................................................................................... 1046 17.4.6 Noise Canceler.................................................................................................... 1048 17.4.7 Example of Use..
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19.2 Input/Output Pins............................................................................................................. 1097 19.3 Register Descriptions ....................................................................................................... 1097 19.3.1 D/A Data Registers 2 and 3 (DADR2 and DADR3)........................................... 1097 19.3.2 D/A Control Register 23 (DACR23) .................................................................. 1098 19.4 Operation ............
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22.3 22.4 22.5 22.6 22.7 22.8 22.9 22.10 22.11 22.12 22.2.2 Flash Memory Data Block Protect Register (FLMDBPR) ................................. 1150 22.2.3 Flash Memory Status Register (FLMSTR)......................................................... 1151 On-Board Programming Mode ........................................................................................ 1152 22.3.1 User Programming Mode.................................................................................... 1153 22.3.
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23.5.1 Notes on Clock Pulse Generator ......................................................................... 1211 23.5.2 Notes on Resonator............................................................................................. 1211 23.5.3 Notes on Board Design ....................................................................................... 1212 Section 24 Power-Down Modes ......................................................................1213 24.1 Register Descriptions ..................
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26.1.5 D/A Conversion Characteristics ......................................................................... 1303 26.1.6 USB Characteristics............................................................................................ 1303 26.1.7 Flash Memory Characteristics ............................................................................ 1304 26.2 Electrical Characteristics for H8S/2454 Group................................................................ 1306 26.2.1 Absolute Maximum Ratings .
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Section 1 Overview 1.1 Features The H8S/2456 Group, H8S/2454 Group, and H8S/2456R Group are CISC (Complex Instruction Set Computer) microprocessors that integrate an H8S/2600 CPU core which has an internal 16-bit architecture and is upward-compatible with Renesas-original H8/300, H8/300H, and H8S CPUs.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Table 1.
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H8S/2456, H8S/2456R, H8S/2454 Group Type CPU Interrupts (sources) Module/ Function MCU operating mode Interrupt controller Section 1 Overview Description • Mode 1: Expanded mode with on-chip ROM disabled, 16-bit bus (MD2 and MD1 pins are low and MD0 pin is high) • Mode 2: Expanded mode with on-chip ROM disabled, 8-bit bus (MD2 pin is low, MD1 pin is high, and MD0 pin is low) • Mode 3: Boot mode (MD2 pin is low and MD1 and MD0 pins are high) • Mode 4: Expanded mode with on-chip ROM enabled,
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Type DMA Module/ Function DMA controller (DMAC) Description • DMA transfer is possible on four channels • Three activation sources (auto-request, on-chip module interrupt, and external request) • Byte or word can be set as the transfer unit • Short address mode or full address mode can be selected • 16-Mbyte address space can be specified directly EXDMA controller • (EXDMAC) • DMA transfer is possible on two channels Two activation source
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H8S/2456, H8S/2456R, H8S/2454 Group Type Clock Module/ Function Clock pulse generator (CPG) Section 1 Overview Description • This LSI has a single on-chip clock pulse generator circuit • Consists of an oscillator, a system-clock PLL circuit, a divider, and a PLL circuit for the USB, and the system clock frequency can be changed System clock (φ) cycle: 8 to 33 MHz • Six power-down modes Divided clock mode, sleep mode, module stop function, all module clock stop mode, software standby mode, and hardw
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Type Timer Module/ Function 16-bit timer pulse unit (TPU) Description • 16-bit timer × 12 channels (general pulse timer unit) • Eight counter input clocks can be selected for each channel • Maximum 16-pulse input/output (when external expanded mode is set) • Maximum 32-pulse input/output (when single-chip mode is set) • Counter clear operation, simultaneous write to multiple timer counters (TCNT), simultaneous clearing by compare match and
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H8S/2456, H8S/2456R, H8S/2454 Group Type Module/ Function Smart Card/SIM Highfunction communications Section 1 Overview Description SCI supports Smart Card (SIM) interface I2C bus interface 2 (IIC2) Synchronous serial communication unit (SSU) USB function module I/O ports • Four channels • Continuous transmission/reception • Start and stop conditions generated automatically in master mode • Selection of acknowledge output levels when receiving • Automatic loading of acknowledge bit when t
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Type Module/ Function Package Description H8S/2456 Group, H8S/2456R Group: • 144-pin QFP package (PLQP0144KA-A) (code: FP-144LV, body size: 20 × 20 mm, pin pitch: 0.50 mm) • 145-pin TLP package (PTLG0145JB-A) (code: body size: 9 × 9 mm, pin pitch: 0.65 mm) H8S/2454 Group: • 120-pin QFP package (PLQP0120LA-A) (code: FP-120BV, body size: 14 × 14 mm, pin pitch: 0.40 mm) • 120-pin QFP package (PLQP0120KA-A) (body size: 16 × 16 mm, pin pitch: 0.
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H8S/2456, H8S/2456R, H8S/2454 Group 1.2 Section 1 Overview List of Products Table 1.2 lists the products and figure 1.1 shows how to read the product type name. Table 1.2 Product Code Lineup Flash RAM Operating Guaranteed Product Type Type Code Memory Size Size Voltage Temperature Range Package Code H8S/2456R R4F24569NVRFQV 256 Kbytes 64 Kbytes 3.0 to 3.6 V R4F24568NVRFQV 256 Kbytes 48 Kbytes 3.0 to 3.6 V R4F24565NVRFQV 128 Kbytes 48 Kbytes 3.0 to 3.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Flash RAM Operating Guaranteed Product Type Type Code Memory Size Size Voltage Temperature Range Package Code H8S/2456 R4F24569NVFQV 256 Kbytes 64 Kbytes 3.0 to 3.6 V R4F24568NVFQV 256 Kbytes 48 Kbytes 3.0 to 3.6 V R4F24565NVFQV 128 Kbytes 48 Kbytes 3.0 to 3.6 V R4S24562NVFQV ⎯ 64 Kbytes 3.0 to 3.6 V R4S24561NVFQV ⎯ 48 Kbytes 3.0 to 3.6 V R4F24569DVFQV 256 Kbytes 64 Kbytes 3.0 to 3.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Flash RAM Operating Guaranteed Product Type Type Code Memory Size Size Voltage Temperature Range Package Code H8S/2454 R4F24549NVFPV 256 Kbytes 64 Kbytes 3.0 to 3.6 V R4F24548NVFPV 256 Kbytes 48 Kbytes 3.0 to 3.6 V R4F24545NVFPV 128 Kbytes 48 Kbytes 3.0 to 3.6 V R4S24542NVFPV ⎯ 64 Kbytes 3.0 to 3.6 V R4S24541NVFPV ⎯ 48 Kbytes 3.0 to 3.6 V R4F24549DVFPV 256 Kbytes 64 Kbytes 3.0 to 3.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Product type name R 4 F 2456 9 N V R FQ V Indicates treatment of outer leads V: Sn-2Bi U: Sn Indicates the package FQ: PLQP0144KA-A LP: PTLG0145JB-A FP: PLQP0120LA-A FA: PLQP0120KA-A Indicates the product group R: H8S/2456R group None: H8S/2456 group or H8S/2454 group Indicates the operating voltage V: 3.0 to 3.6 V None: 4.5 to 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Port A Port B Peripheral address bus Bus controller Peripheral data bus Internal data bus Internal address bus Port C PE7/D7/AD7 PE6/D6/AD6 PE5/D5/AD5 PE4/D4/AD4 PE3/D3/AD3 PE2/D2/AD2 PE1/D1/AD1 PE0/D0/AD0 Port F DMAC ROM (flash memory) PB7/A15/TIOCB8/TCLKH PB6/A14/TIOCA8 PB5/A13/TIOCB7/TCLKG PB4/A12/TIOCA7 PB3/A11/TIOCD6/TCLKF PB2/A10/TIOCC6/TCLKE PB1/A9/TIOCB6 PB0/A8/TIOCA6 PC7/A7/TIOCB11 PC6/A6/TIOCA11 PC5/A5/TIOCB10 PC4/A4/TIOCA10 PC3/A3/TIOCD9 PC2/A2/TIOCC
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Port G P85/PO5-B/TIOCB4-B/TMO1-B/SCK3 P83/PO3-B/TIOCD3-B/TMCI1-B/RxD3 P81/PO1-B/TIOCB3-B/TMRI1-B/TxD3 Port A PG6/BREQ-A PG5/BACK-A PG4/BREQO-A/CS4 PG3/CS3/RAS3 PG2/CS2/RAS2 PG1/CS1 PG0/CS0 Port B DMAC ROM (flash memory) Periheral address bus DTC PA7/A23/CS7/IRQ7-A/SSO0-B PA6/A22/IRQ6-A/SSI0-B PA5/A21/IRQ5-A/SSCK0-B PA4/A20/IRQ4-A/SCS0-B PA3/A19/SCK4-B PA2/A18/RxD4-B PA1/A17/TxD4-B PA0/A16 PB7/A15/TIOCB8/TCLKH PB6/A14/TIOCA8 PB5/A13/TIOCB7/TCLKG PB4/A12/TIOCA7 PB3/A11/TIOCD6/TCLKF PB2/A10/TIOCC6/TCL
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H8S/2456, H8S/2456R, H8S/2454 Group Pin Description 1.4.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview 1 2 3 4 5 6 7 8 9 10 11 12 13 A Vss MD1 MD0 P32 P35 P50 AVss P94 P90 P44 P40 PG2 PG3 B MD2 Vcc P31 P34 P51 PG4 P93 P47 P45 P42 AVcc Vref PG1 C PC0 P80 PC1 P30 P33 P52 PG5 P92 P46 P43 P41 PG0 P65 D PC4 PC2 PC3 P53 PG6 P97 P96 P95 P91 P63 PJ0 P64 STBY E PC7 Vss PC5 PB0 NC Vss Vcc PJ1 Vcc F PB3 PC6 PB1 Vss PF7 Vss XTAL EXTAL G PB6 PB2 PA0 PB4 PF6 RES PF5 PLLVss
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H8S/2456, H8S/2456R, H8S/2454 Group 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PG1/CS1 PG0/CS0 STBY VSS P81/PO1-B/TIOCB3-B/TMRI1-B/TxD3 P83/PO3-B/TIOCD3-B/TMCI1-B/RxD3 VCC VCC EXTAL XTAL VSS PF7/φ PLLVSS RES PLLVCC PF6/AS/AH PF5/RD PF4/HWR PF3/LWR/SSO0-C PF2/CS6/LCAS/SSI0-C PF1/CS5/UCAS/SSCK0-C PF0/WAIT-A/OE-A/ADTRG0-B/SCS0-C PD7/D15/AD15 PD6/D14/AD14 PD5/D13/AD13 PD4/D12/AD12 PD3/D11/AD11 PD2/D10/AD10 PD1/D9/AD9 PD0/D8/AD8 Section 1 Overview 91 92 93 94 95
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview 1.4.2 Pin Assignments in Each Operating Mode Table 1.3 Pin Assignments in Each Operating Mode of H8S/2456 Group and H8S/2456R Group Pin No.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Pin No.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Pin No.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Pin No.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Pin No.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Pin No.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Pin No.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Pin No.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Pin No.
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H8S/2456, H8S/2456R, H8S/2454 Group Table 1.4 Section 1 Overview Pin Assignments in Each Operating Mode of H8S/2454 Group Pin No.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Pin No.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Pin No.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Pin No.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Pin No.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Pin No.
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H8S/2456, H8S/2456R, H8S/2454 Group 1.4.3 Section 1 Overview Pin Functions Table 1.5 Pin Functions Pin No. H8S/2454 H8S/2456, H8S/2456R PLQP0120LA-A, Type Symbol PLQP0144KA-A PTLG0145JB-A PLQP0120KA-A I/O Function Power supply VCC 4, 72, 98, 99 B2, N12, E11, E13 2, 60, 83, 84 Input For connection to the power supply. VCC pins should be connected to the system power supply.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Pin No. H8S/2454 H8S/2456, H8S/2456R PLQP0120LA-A, Type Symbol PLQP0144KA-A PTLG0145JB-A PLQP0120KA-A I/O Function Clock XTAL 96 F12 81 Input For connection to a crystal oscillator. See section 23, Clock Pulse Generator, for typical connection diagrams for a crystal resonator and external clock input. EXTAL 97 F13 82 Input For connection to a crystal oscillator. The EXTAL pin can also input an external clock.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Pin No. H8S/2454 H8S/2456, H8S/2456R PLQP0120LA-A, Type Symbol PLQP0144KA-A PTLG0145JB-A PLQP0120KA-A I/O Address bus A23 to A0 31 to 26, 24 to 19, 17 to 11, 9 to 5 J3, K2, J1, K4, H3, J2, J4, G3, H2, G1, H4, G4, F1, G2, F3, E4, E1, F2, E3, D1, D3, D2, C3, C1 29 to 23, 21 to 18, 16 to 9, 7 to 3 Output These pins output an address.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Pin No. H8S/2454 H8S/2456, H8S/2456R PLQP0120LA-A, Type Symbol PLQP0120KA-A I/O Bus control BREQO-A 130 BREQO-B 133 B6 106 A6 109 Output External bus request signal when the internal bus master accesses an external space in the external bus release state. BACK-A BACK-B 131 C7 107 135 C6 111 UCAS 85 H12 70 Output Upper column address strobe signal for accessing the 16-bit DRAM space.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Pin No.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Pin No. H8S/2454 H8S/2456, H8S/2456R PLQP0120LA-A, Type Symbol PLQP0144KA-A PTLG0145JB-A PLQP0120KA-A I/O EXDMA controller (EXDMAC) *2 EDRAK3 49 L5 ⎯ EDRAK2 48 K6 Output These signals notify an external device of acceptance and start of execution of a DMA transfer request.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Pin No. H8S/2454 H8S/2456, H8S/2456R PLQP0120LA-A, Type Symbol 16-bit timer TIOCB4-A pulse TIOCA4-B unit (TPU) TIOCB4-B PLQP0144KA-A PTLG0145JB-A PLQP0120KA-A I/O 56 N7 47 135 C6 111 Input/ TGRA_4 and TGRB_4 input capture output input/output compare output/PWM output pins.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Pin No. H8S/2454 H8S/2456, H8S/2456R PLQP0120LA-A, Type Symbol PLQP0144KA-A PTLG0145JB-A PLQP0120KA-A I/O Programmable pulse generator (PPG) PO15 to PO8 49 to 42 L5, K6, K5, N4, M5, L4, M4, N3 41 to 34 Output Pulse output pins.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Pin No. H8S/2454 H8S/2456, H8S/2456R PLQP0120LA-A, Type Symbol PLQP0144KA-A PTLG0145JB-A PLQP0120KA-A I/O Serial communication interface (SCI)/ Smart Card interface (SCI_0 with IrDA function) TxD4-B 24 J4 23 Output Data output pins.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Pin No. H8S/2454 H8S/2456, H8S/2456R PLQP0120LA-A, Type Symbol PLQP0144KA-A PTLG0145JB-A PLQP0120KA-A I/O Synchronous serial communication unit (SSU) SSO0-A 46 N4 38 SSO0-B 31 J3 29 Input/ Data input/output pins.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Pin No. H8S/2454 H8S/2456, H8S/2456R PLQP0120LA-A, Type Symbol PLQP0144KA-A PTLG0145JB-A PLQP0120KA-A I/O Function A/D converter, D/A converter AVCC 111 B11 93 Input Analog power-supply pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (VCC). AVSS 129 A7 105 Input Ground pin for the A/D converter and D/A converter.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 1 Overview Pin No. H8S/2454 H8S/2456, H8S/2456R PLQP0120LA-A, Type I/O ports Symbol PLQP0144KA-A PTLG0145JB-A PLQP0120KA-A I/O Function P97* , P96*2 128 , 127 D6, D7 ⎯ Input P95, P94, 126, 125 D8, A8 104, 103 8-bit input/output pins in the H8S/2456 Group and H8S/2456R Group. P93 to P90*2 124 to 121 B7, C8, D9, A9 ⎯ PA7 to PA0 31 to 26, 24, 23 J3, K2, J1, K4, H3, J2, J4, G3 29 to 23, 21 Input/ 8-bit input/output pins.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 2 CPU Section 2 CPU The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2600 CPU. The usable modes and address spaces differ depending on the product.
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Section 2 CPU H8S/2456, H8S/2456R, H8S/2454 Group • High-speed operation All frequently-used instructions execute in one or two states 8/16/32-bit register-register add/subtract: 1 state 8 × 8-bit register-register multiply: 2 states 16 ÷ 8-bit register-register divide: 12 states 16 × 16-bit register-register multiply: 3 states 32 ÷ 16-bit register-register divide: 20 states • Two CPU operating modes Normal mode* Advanced mode Note: * Normal mode is not available in this LSI.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 2 CPU Execution States Instruction Mnemonic H8S/2600 H8S/2000 MULXU MULXU.B Rs, Rd 2* 12 MULXU.W Rs, ERd 2* 20 MULXS.B Rs, Rd 3* 13 MULXS.W Rs, ERd 3* 21 CLRMAC CLRMAC 1* Not supported LDMAC LDMAC ERs, MACH 1* LDMAC ERs, MACL 1* STMAC STMAC MACH, ERd 1* STMAC MACL, ERd 1* MULXS Note: 2.1.2 * The number of execution states is incremented following a MAC instruction.
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Section 2 CPU H8S/2456, H8S/2456R, H8S/2454 Group • Higher speed Basic instructions execute twice as fast. Note: Normal mode is not available in this LSI. 2.1.3 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements. • Additional control register One 8-bit and two 32-bit control registers have been added. • Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced.
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H8S/2456, H8S/2456R, H8S/2454 Group 2.2 Section 2 CPU CPU Operating Modes The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-Kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. • Address Space The H8S/2600 CPU provides linear access to a maximum 64-Kbyte address space.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 2 CPU H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Reset exception vector (Reserved for system use) (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2.1 Exception Vector Table (Normal Mode) SP PC (16 bits) EXR*1 SP Reserved*1 *3 (SP*2 ) CCR CCR*3 PC (16 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used, it is not stored on the stack.
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H8S/2456, H8S/2456R, H8S/2454 Group 2.2.2 Section 2 CPU Advanced Mode • Address Space Linear access is provided to a 16-Mbyte maximum address space. • Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. • Instruction Set All instructions and addressing modes can be used.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 2 CPU The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF.
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H8S/2456, H8S/2456R, H8S/2454 Group 2.3 Section 2 CPU Address Space Figure 2.5 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-Kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, see section 3, MCU Operating Modes.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 2 CPU 2.4 Registers The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8bit extended register (EXR), an 8-bit condition code register (CCR), and a 64-bit multiplyaccumulate register (MAC).
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H8S/2456, H8S/2456R, H8S/2454 Group 2.4.1 Section 2 CPU General Registers The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 2 CPU Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.) 2.4.
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H8S/2456, H8S/2456R, H8S/2454 Group 2.4.4 Section 2 CPU Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 2 CPU Bit Bit Name Initial Value R/W Description 2 Z Undefined R/W Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 V Undefined R/W Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise. 0 C Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise.
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H8S/2456, H8S/2456R, H8S/2454 Group 2.5 Section 2 CPU Data Formats The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.9 shows the data formats in general registers.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 2 CPU Data Type Register Number Word data Rn Data Format 15 0 MSB Word data 15 0 MSB Longword data LSB En LSB ERn 31 16 15 MSB En 0 Rn LSB Legend: ERn En Rn RnH RnL MSB LSB : General register ER : General register E : General register R : General register RH : General register RL : Most significant bit : Least significant bit Figure 2.9 General Register Data Formats (2) Page 60 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group 2.5.2 Section 2 CPU Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 2 CPU 2.6 Instruction Set The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in table 2.1. Table 2.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 2 CPU 2. Bcc is the general name for conditional branch instructions. 3. Cannot be used in this LSI. 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 2 CPU Symbol Description → Move ∼ NOT (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Table 2.
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H8S/2456, H8S/2456R, H8S/2454 Group Table 2.4 Section 2 CPU Arithmetic Operations Instructions (1) Instruction Size* Function ADD B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 2 CPU Table 2.4 Arithmetic Operations Instructions (2) Instruction Size*1 Function DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result.
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H8S/2456, H8S/2456R, H8S/2454 Group Table 2.5 Section 2 CPU Logic Operations Instructions Instruction Size* Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 2 CPU Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0.
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H8S/2456, H8S/2456R, H8S/2454 Group Table 2.7 Section 2 CPU Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C ⊕ ( of ) → C Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ [~ ( of )] → C Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 2 CPU Table 2.8 Branch Instructions Instruction Size Function Bcc ⎯ Branches to a specified address if a specified condition is true. The branching conditions are listed below.
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H8S/2456, H8S/2456R, H8S/2454 Group Table 2.9 Section 2 CPU System Control Instructions Instruction Size* Function TRAPA ⎯ Starts trap-instruction exception handling. RTE ⎯ Returns from an exception-handling routine. SLEEP ⎯ Causes a transition to a power-down state. LDC B/W (EAs) → CCR, (EAs) → EXR Moves the contents of a general register or memory, or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction Size Function EEPMOV.B ⎯ if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; EEPMOV.W ⎯ if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 2 CPU (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op rn rm MOV.B @(d:16, Rn), Rm, etc. EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc. Figure 2.11 Instruction Formats (Examples) R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 2 CPU 2.7 Addressing Modes and Effective Address Calculation The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. The usable address modes are different in each instruction. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect.
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H8S/2456, H8S/2456R, H8S/2454 Group 2.7.3 Section 2 CPU Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction code, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. 2.7.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 2 CPU Table 2.12 Absolute Address Access Ranges Normal Mode* Absolute Address Data address 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF 16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF 32 bits (@aa:32) Program instruction address Note: 2.7.6 * Advanced Mode H'000000 to H'FFFFFF 24 bits (@aa:24) Not available in this LSI.
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H8S/2456, H8S/2456R, H8S/2454 Group 2.7.8 Section 2 CPU Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode).
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H8S/2456, H8S/2456R, H8S/2454 Group Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Note: Normal mode is not available in this LSI. Table 2.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 2 CPU Table 2.13 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address @aa:8 31 op @aa:16 31 op 0 H'FFFF 24 23 16 15 0 Don't care Sign extension abs @aa:24 31 op 8 7 24 23 Don't care abs 24 23 0 Don't care abs @aa:32 op 31 6 Immediate #xx:8/#xx:16/#xx:32 op 7 0 24 23 Don't care abs Operand is immediate data.
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Section 2 CPU 2.8 H8S/2456, H8S/2456R, H8S/2454 Group Processing States The H8S/2600 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. • Reset State The CPU and on-chip peripheral modules are all initialized and stop. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 2 CPU End of bus request Bus request pt ion ha ex nd ce lin pt g io n ha nd lin g ce En d or ex st f of ue d En Re q Exception handling state n Bus-released state Sleep mode t ues q t re rrup Inte =0 BY SS EEP tion SL truc ins io = 1 ruct BY nst SS EP i E SL of bu s re Bu qu sr es eq t ue st Program execution state External interrupt request Software standby mode RES = High Reset state*1 STBY = High, RES = Low Reset state Hardware st
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Section 2 CPU 2.9 Usage Note 2.9.1 Usage Notes on Bit-wise Operation Instructions H8S/2456, H8S/2456R, H8S/2454 Group The BSET, BCLR, BNOT, BST, and BIST instructions are used to read data in byte-wise, operate the data in bit-wise, and write the result of the bit-wise operation in bit-wise again. Therefore, special care is necessary to use these instructions for the registers and the ports that include writeonly bit.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Operating Mode Selection The H8S/2456 Group, H8S/2454 Group, and H8S/2456R Group have five operating modes (modes 1 to 4 and 7). The operating mode is selected by the setting of mode pins (MD2 to MD0). Modes 1, 2, and 4 are externally expanded modes in which the CPU can access an external memory and peripheral devices.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 3 MCU Operating Modes 3.2 Register Descriptions The following registers are related to operating mode setting. • • Mode control register (MDCR) System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR monitors the current operating mode of this LSI. Bit Bit Name Initial Value R/W Descriptions 7 to 3 ⎯ All 0 ⎯ Reserved These bits are always read as 0 and cannot be modified.
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H8S/2456, H8S/2456R, H8S/2454 Group 3.2.2 Section 3 MCU Operating Modes System Control Register (SYSCR) SYSCR selects saturation operation for the MAC instruction, controls CPU access to the flash memory control registers, sets the external bus mode, and enables or disables on-chip RAM. Bit Bit Name Initial Value R/W Descriptions 7, 6 ⎯ All 1 R/W Reserved 5 MACS 0 R/W MAC Saturation Operation Control The initial value should not be modified.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 3 MCU Operating Modes Bit Bit Name Initial Value R/W Descriptions 1 EXPE ⎯ R/W External Bus Mode Enable Sets the external bus mode. In modes 1, 2, and 4, this bit is fixed at 1 and cannot be modified. In modes 3 and 7, this bit can be read from and written to. Writing 0 to this bit when its value is 1 should only be carried out when an external bus cycle is not being executed.
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H8S/2456, H8S/2456R, H8S/2454 Group 3.3 Operating Mode Descriptions 3.3.1 Mode 1 Section 3 MCU Operating Modes The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A to C function as an address bus, ports D and E function as a data bus, and parts of ports F to H function as bus control signals. The initial bus mode immediately after a reset is 16 bits, with 16-bit access to all areas.
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Section 3 MCU Operating Modes 3.3.4 H8S/2456, H8S/2456R, H8S/2454 Group Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. The program in the on-chip ROM connected to the first half of area 0 is executed. Ports A to C function as input ports immediately after a reset, but can be set to function as an address bus depending on each port register setting. Port D functions as a data bus and parts of ports F to H function as bus control signals.
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H8S/2456, H8S/2456R, H8S/2454 Group 3.3.6 Section 3 MCU Operating Modes Pin Functions Table 3.2 shows the pin functions in each operating mode. Table 3.
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Section 3 MCU Operating Modes 3.4 H8S/2456, H8S/2456R, H8S/2454 Group Memory Map in Each Operating Mode Figures 3.1 to 3.5 show memory maps in each operating mode. Page 90 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 3 MCU Operating Modes RAM: 64 Kbytes/48 Kbytes ROM: 256 Kbytes RAM: 64 Kbytes/48 Kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) Mode 3 (Boot mode) H'000000 H'000000 On-chip ROM H'040000 Reserved area*4 H'080000 External address space External address space/ Reserved area*2*4 H'F00000 Data flash area 8 Kbytes H'F02000 External address space/ Reserved area*2*4 H'FE8000 H'FEC000 H'FF0000 H'FFC000 H'FFD000 H'FE8000 Reserved area*4 Reserved
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H8S/2456, H8S/2456R, H8S/2454 Group Section 3 MCU Operating Modes ROM: 256 Kbytes RAM: 64 Kbytes / 48 Kbytes Mode 4 (Expanded mode with on-chip ROM enabled) ROM: 256 Kbytes RAM: 64 Kbytes / 48 Kbytes Mode 7 (Single-chip activation expanded mode with on-chip ROM enabled) H'000000 H'000000 On-chip ROM On-chip ROM H'040000 H'040000 Reserved area*4 Reserved area*4 H'080000 H'080000 External address space/ Reserved area*2*4 External address space H'F00000 H'F00000 Data flash area 8 Kbytes Data fla
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H8S/2456, H8S/2456R, H8S/2454 Group Section 3 MCU Operating Modes RAM: 48 Kbytes ROM: 128 Kbytes RAM: 48 Kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 Mode 3 (Boot mode) H'000000 On-chip ROM H'020000 Reserved area*4 H'080000 External address space External address space/ Reserved area*2*4 H'F00000 Data flash area 8 Kbytes H'F02000 External address space/ Reserved area*2*4 H'FE8000 H'FE8000 Reserved area*4 Reserved area*4 H'FF0000 H'FF0000 On-chip RAM/ External address
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H8S/2456, H8S/2456R, H8S/2454 Group Section 3 MCU Operating Modes ROM: 128 Kbytes RAM: 48 Kbytes Mode 4 (Expanded mode with on-chip ROM enabled) ROM: 128 Kbytes RAM: 48 Kbytes Mode 7 (Single-chip activation expanded mode with on-chip ROM enabled) H'000000 H'000000 On-chip ROM H'020000 On-chip ROM H'020000 Reserved area*4 Reserved area*4 H'080000 H'080000 External address space/ Reserved area*2*4 External address space H'F00000 H'F00000 Data flash area 8 Kbytes Data flash area 8 Kbytes H'F020
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H8S/2456, H8S/2456R, H8S/2454 Group Section 3 MCU Operating Modes RAM: 64 Kbytes /48 Kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 External address space H'FE8000 H'FEC000 H'FF0000 H'FFC000 H'FFD000 Reserved area*2 On-chip RAM/External address space/ Reserved area*1*3 On-chip RAM/External address space*1*3 Reserved area*2 External address space H'FFFA00 Internal I/O registers H'FFFF00 External address space H'FFFF20 H'FFFFFF Internal I/O registers Notes: 1.
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Section 3 MCU Operating Modes Page 96 of 1408 H8S/2456, H8S/2456R, H8S/2454 Group R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 4 Exception Handling Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, illegal instruction, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 4 Exception Handling 4.2 Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Since the usable modes differ depending on the product, for details on each product, refer to section 3, MCU Operating Modes. Table 4.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 4 Exception Handling Vector Address*1 Vector Number Normal Mode*2 Advanced Mode IRQ7 IRQ8*5 23 H'002E to H'002F H'005C to H'005F 24 H'0030 to H'0031 H'0060 to H'0063 IRQ9* 25 H'0032 to H'0033 H'0064 to H'0067 IRQ10*5 IRQ11*5 26 H'0034 to H'0035 H'0068 to H'006B 27 H'0036 to H'0037 H'006C to H'006F IRQ12*5 IRQ13*5 28 H'0038 to H'0039 H'0070 to H'0073 29 H'003A to H'003B H'0074 to H'0077 IRQ14*5 30 H'003C to H'003D H'0078 to H'007B
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Section 4 Exception Handling 4.3 H8S/2456, H8S/2456R, H8S/2454 Group Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 15 ms at power-up. To reset this LSI during operation, hold the RES pin low for at least 2 ms. A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 4 Exception Handling Vector fetch Prefetch of first Internal processing program instruction (1) (3) φ RES Internal address bus (5) Internal read signal Internal write signal Internal data bus High (2) (4) (6) (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Figure 4.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 4 Exception Handling Internal processing Vector fetch * * Prefetch of first program instruction * φ RES Address bus (1) (3) (5) RD HWR, LWR D15 to D0 High (2) (4) (6) (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Note: * Seven program wait states are inserted.
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H8S/2456, H8S/2456R, H8S/2454 Group 4.4 Section 4 Exception Handling Trace Exception Handling Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details on interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is not affected by interrupt masking. Table 4.
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Section 4 Exception Handling 4.5 H8S/2456, H8S/2456R, H8S/2454 Group Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed interrupt control. The source to start interrupt exception handling and the vector address differ depending on the product. For details, refer to section 5, Interrupt Controller.
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H8S/2456, H8S/2456R, H8S/2454 Group 4.6 Section 4 Exception Handling Trap Instruction Exception Handling Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling is as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended register (EXR) are saved in the stack. 2.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 4 Exception Handling 4.7 Illegal Instruction Exception Handling Illegal instruction exception handling starts when the CPU executing an illegal instruction code is detected. Illegal instruction exception handling can be executed at all times in the program execution state. The illegal instruction exception handling is as follows: 1. The values in the PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3.
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H8S/2456, H8S/2456R, H8S/2454 Group 4.8 Section 4 Exception Handling Stack Status after Exception Handling Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling. Normal Modes*2 SP EXR Reserved*1 SP CCR CCR CCR*1 CCR*1 PC (16 bits) PC (16 bits) Interrupt control mode 0 Interrupt control mode 2 Advanced Modes SP EXR Reserved*1 SP CCR PC (24 bits) Interrupt control mode 0 CCR PC (24 bits) Interrupt control mode 2 Notes: 1.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 4 Exception Handling 4.9 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the interrupt control register (INTCR). • Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1.
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H8S/2456, H8S/2456R, H8S/2454 Group 5.2 Section 5 Interrupt Controller Input/Output Pins Table 5.1 shows the pin configuration of the interrupt controller. Table 5.1 Pin Configuration Name I/O Function NMI Input Nonmaskable external interrupt Rising or falling edge can be selected. IRQ15-A to IRQ0-A* IRQ15-B to IRQ0-B* Note: * Input Maskable external interrupts Rising, falling, or both edges, or level sensing, can be selected. IRQ7-A to IRQ0-A and IRQ7-B to IRQ0-B in the H8S/2454 Group.
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Section 5 Interrupt Controller 5.3 H8S/2456, H8S/2456R, H8S/2454 Group Register Descriptions The interrupt controller has the following registers.
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H8S/2456, H8S/2456R, H8S/2454 Group 5.3.1 Section 5 Interrupt Controller Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI. Bit Bit Name Initial Value R/W Description 7, 6 ⎯ All 0 ⎯ Reserved These bits are always read as 0 and the initial value should not be changed. 5 INTM1 0 R/W Interrupt Control Select Mode 1 and 0 4 INTM0 0 R/W These bits select either of two interrupt control modes for the interrupt controller.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 5 Interrupt Controller 5.3.2 Interrupt Priority Registers A to N (IPRA to IPRN) IPR are eleven 16-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between interrupt sources and IPR settings is shown in table 5.2 (Interrupt Sources, Vector Addresses, and Interrupt Priorities).
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H8S/2456, H8S/2456R, H8S/2454 Group Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 7 ⎯ 0 ⎯ Reserved This bit is always read as 0 and the initial value should not be changed.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 5 Interrupt Controller 5.3.3 IRQ Enable Register (IER) IER controls enabling and disabling of interrupt requests IRQ15 to IRQ0. Bit Bit Name Initial Value R/W Description 15 IRQ15E 0 R/W IRQ15 Enable* The IRQ15 interrupt request is enabled when this bit is 1. 14 IRQ14E 0 R/W IRQ14 Enable* The IRQ14 interrupt request is enabled when this bit is 1. 13 IRQ13E 0 R/W IRQ13 Enable* The IRQ13 interrupt request is enabled when this bit is 1.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 5 IRQ5E 0 R/W IRQ5 Enable The IRQ5 interrupt request is enabled when this bit is 1. 4 IRQ4E 0 R/W IRQ4 Enable The IRQ4 interrupt request is enabled when this bit is 1. 3 IRQ3E 0 R/W IRQ3 Enable The IRQ3 interrupt request is enabled when this bit is 1. 2 IRQ2E 0 R/W IRQ2 Enable The IRQ2 interrupt request is enabled when this bit is 1.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 5 Interrupt Controller 5.3.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCR select the source that generates an interrupt request at pins IRQ15 to IRQ0.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 9 IRQ12SCB 0 R/W IRQ12 Sense Control B 8 IRQ12SCA 0 R/W IRQ12 Sense Control A 00: Interrupt request generated at IRQ12 input low level 01: Interrupt request generated at falling edge of IRQ12 input 10: Interrupt request generated at rising edge of IRQ12 input 11: Interrupt request generated at both falling and rising edges of IRQ12 input 7 IRQ11SCB 0 R/W IRQ11 Sense Control B 6
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H8S/2456, H8S/2456R, H8S/2454 Group Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 3 IRQ9SCB 0 R/W IRQ9 Sense Control B 2 IRQ9SCA 0 R/W IRQ9 Sense Control A 00: Interrupt request generated at IRQ9 input low level 01: Interrupt request generated at falling edge of IRQ9 input 10: Interrupt request generated at rising edge of IRQ9 input 11: Interrupt request generated at both falling and rising edges of IRQ9 input 1 IRQ8SCB 0 R/W IRQ8 Sense Control B 0 IRQ8SCA
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H8S/2456, H8S/2456R, H8S/2454 Group • Section 5 Interrupt Controller ISCRL Bit Bit Name Initial Value R/W Description 15 IRQ7SCB 0 R/W IRQ7 Sense Control B 14 IRQ7SCA 0 R/W IRQ7 Sense Control A 00: Interrupt request generated at IRQ7 input low level 01: Interrupt request generated at falling edge of IRQ7 input 10: Interrupt request generated at rising edge of IRQ7 input 11: Interrupt request generated at both falling and rising edges of IRQ7 input 13 IRQ6SCB 0 R/W IRQ6 Sense Control B
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H8S/2456, H8S/2456R, H8S/2454 Group Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 9 IRQ4SCB 0 R/W IRQ4 Sense Control B 8 IRQ4SCA 0 R/W IRQ4 Sense Control A 00: Interrupt request generated at IRQ4 input low level 01: Interrupt request generated at falling edge of IRQ4 input 10: Interrupt request generated at rising edge of IRQ4 input 11: Interrupt request generated at both falling and rising edges of IRQ4 input 7 IRQ3SCB 0 R/W IRQ3 Sense Control B 6 IRQ3SCA
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H8S/2456, H8S/2456R, H8S/2454 Group Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 3 IRQ1SCB 0 R/W IRQ1 Sense Control B 2 IRQ1SCA 0 R/W IRQ1 Sense Control A 00: Interrupt request generated at IRQ1 input low level 01: Interrupt request generated at falling edge of IRQ1 input 10: Interrupt request generated at rising edge of IRQ1 input 11: Interrupt request generated at both falling and rising edges of IRQ1 input 1 IRQ0SCB 0 R/W IRQ0 Sense Control B 0 IRQ0SCA
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H8S/2456, H8S/2456R, H8S/2454 Group Section 5 Interrupt Controller 5.3.5 IRQ Status Register (ISR) ISR is an IRQ15 to IRQ0 interrupt request flag register.
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H8S/2456, H8S/2456R, H8S/2454 Group 5.3.6 Section 5 Interrupt Controller IRQ Pin Select Register (ITSR) ITSR selects input pins IRQ15 to IRQ0. • H8S/2456 Group Bit Bit Name Initial Value R/W Description 15 ITS15 0 R/W Selects the IRQ15 input pin. 0: PF2/IRQ15-A selected 1: P27/IRQ15-B selected 14 ITS14 0 R/W Selects the IRQ14 input pin. 0: PF1/IRQ14-A selected 1: P26/IRQ14-B selected 13 ITS13 0 R/W Selects the IRQ13 input pin.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 5 ITS5 0 R/W Selects the IRQ5 input pin. 0: PA5/IRQ5-A selected 1: P85/IRQ5-B selected 4 ITS4 0 R/W Selects the IRQ4 input pin. 0: PA4/IRQ4-A selected 1: P84/IRQ4-B selected 3 ITS3 0 R/W Selects the IRQ3 input pin. 0: P53/IRQ3-A selected 1: P83/IRQ3-B selected 2 ITS2 0 R/W Selects the IRQ2 input pin.
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H8S/2456, H8S/2456R, H8S/2454 Group • Bit Section 5 Interrupt Controller H8S/2454 Group Bit Name 15 to 8 ⎯ Initial Value R/W Description All 0 Reserved R/W The initial value should not be changed. 7 ITS7 0 R/W Selects the IRQ7 input pin. 0: PA7/IRQ7-A selected 1: P47/IRQ7-B selected 6 ITS6 0 R/W Selects the IRQ6 input pin. 0: PA6/IRQ6-A selected 1: P46/IRQ6-B selected 5 ITS5 0 R/W Selects the IRQ5 input pin.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 5 Interrupt Controller 5.3.7 Software Standby Release IRQ Enable Register (SSIER) SSIER selects the IRQ pins used to recover from the software standby state. Bit Bit Name Initial Value R/W Description 15 SSI15* 0 R/W Software Standby Release IRQ Setting 14 SSI14* 0 R/W 13 SSI13* 0 R/W These bits select the IRQn pins used to recover from the software standby state.
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H8S/2456, H8S/2456R, H8S/2454 Group 5.4 Interrupt Sources 5.4.1 External Interrupts Section 5 Interrupt Controller The H8S/2456 Group and H8S/2456R Group each have seventeen external interrupts: NMI and IRQ15 to IRQ0. The H8S/2454 Group has nine external interrupts: NMI and IRQ7 to IRQ0. These interrupts can be used to restore the chip from software standby mode.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 5 Interrupt Controller IRQnE IRQnSCA, IRQnSCB Edge/ level detection circuit IRQn input IRQnF S Q IRQn interrupt request R Clear signal Note: n = 0 to 15 for H8S/2456 Group and H8S/2456R Group, n = 0 to 7 for H8S/2454 Group Figure 5.2 Block Diagram of IRQ Interrupts 5.4.
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H8S/2456, H8S/2456R, H8S/2454 Group 5.5 Section 5 Interrupt Controller Interrupt Exception Handling Vector Table Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. When interrupt control mode 2 is set, priorities among modules can be set by means of the IPR. Modules set at the same priority will conform to their default priorities. Priorities within a module are fixed. Table 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 5 Interrupt Controller Vector 1 Address* Origin of Interrupt Source Vector Advanced Number Mode IPR Priority DTC Activation DMAC Activation Refresh controller CMI 35 H'008C IPRE2 to IPRE0 High ⎯ ⎯ ⎯ Reserved for 36 system use 37 H'0090 IPRF14 to IPRF12 ⎯ ⎯ ⎯ ⎯ ADI0 38 H'0098 Reserved for 39 system use H'009C ⎯ ⎯ TGI0A 40 H'00A0 TGI0B 41 H'00A4 ⎯ TGI0C 42 H'00A8 ⎯ TGI0D 43 H'00AC TCI0V 44 H'00B0 ⎯ ⎯ Reserved for 45
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H8S/2456, H8S/2456R, H8S/2454 Group Interrupt Source TPU_3 TPU_4 TPU_5 TMR_0 TMR_1 Origin of Interrupt Source Vector 1 Address* Vector Advanced Number Mode IPR Priority DTC Activation DMAC Activation IPRG10 to IPRG8 High ⎯ ⎯ Reserved for 61 system use 62 H'00F4 H'00F8 ⎯ ⎯ 63 H'00FC ⎯ ⎯ TGI4A 64 H'0100 TGI4B 65 H'0104 TCI4V 66 H'0108 ⎯ ⎯ TCI4U 67 H'010C ⎯ ⎯ TGI5A 68 H'0110 TGI5B 69 H'0114 TCI5V 70 H'0118 ⎯ ⎯ TCI5U 71 H'011C ⎯ ⎯ CMIA0 72 H'0120 CMIB0
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H8S/2456, H8S/2456R, H8S/2454 Group Section 5 Interrupt Controller Origin of Interrupt Source Interrupt Source Vector 1 Address* Vector Number Advanced Mode IPR Priority H'0150 IPRH0 to IPRH0 High ⎯ ⎯ IPRI14 to IPRI12 ⎯ H'0158 IPRI10 to IPRI8 ⎯ ⎯ 87 H'015C IPRI6 to IPRI4 ⎯ ⎯ ERI0 88 H'0160 IPRI2 to IPRI0 ⎯ ⎯ RXI0 89 H'0164 TXI0 90 H'0168 TEI0 91 H'016C ⎯ ⎯ ERI1 92 H'0170 ⎯ ⎯ RXI1 93 H'0174 ⎯ ⎯ ⎯ ⎯ H'0154 EXDMTEND2 86 EXDMTEND3 2 SCI_1 SCI_2 SCI_3
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H8S/2456, H8S/2456R, H8S/2454 Group Section 5 Interrupt Controller Vector 1 Address* Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR Priority A/D_1 ADI1 112 H'01C0 IPRK10 to IPRK8 High IIC2_0 IIC2_1 TPU_6 TPU_7 TPU_8 TPU_9 DTC Activation DMAC Activation ⎯ ⎯ Reserved for 113 system use 114 H'01C4 ⎯ H'01C8 ⎯ ⎯ 115 H'01CC ⎯ ⎯ 116 H'01D0 ⎯ ⎯ Reserved for 117 system use H'01D4 ⎯ ⎯ IICI1 118 H'01D8 ⎯ ⎯ Reserved for 119 system use H'01DC
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H8S/2456, H8S/2456R, H8S/2454 Group Section 5 Interrupt Controller Vector 1 Address* Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR Priority TPU_10 TGI10A 138 H'0228 IPRL2 to IPRL0 High TGI10B 139 H'022C TCI10V 140 H'0230 ⎯ ⎯ TCI10U 141 H'0234 ⎯ ⎯ TGI11A 142 H'0238 TGI11B 143 H'023C TCI11V 144 H'0240 ⎯ ⎯ TCI11U 145 H'0244 ⎯ ⎯ USBINTN0 146 H'0248 USBINTN1 147 H'024C ⎯ USBINTN2 148 H'0250 ⎯ ⎯ USBINTN3 149 H'0254 ⎯ ⎯ USBI
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H8S/2456, H8S/2456R, H8S/2454 Group Interrupt Source ⎯ Origin of Interrupt Source Section 5 Interrupt Controller Vector 1 Address* Vector Number Advanced Mode IPR Priority DTC Activation DMAC Activation H'0278 IPRN10 to IPRN8 High ⎯ ⎯ ⎯ Reserved for 158 system use 159 H'027C ⎯ 160 H'0280 ⎯ ⎯ 161 H'0284 ⎯ ⎯ 162 H'0288 ⎯ ⎯ 163 H'028C ⎯ ⎯ 164 H'0290 ⎯ ⎯ 165 H'0294 ⎯ ⎯ 166 H'0298 ⎯ ⎯ 167 H'029C ⎯ ⎯ 168 H'02A0 ⎯ ⎯ 169 H'02A4 ⎯ ⎯ Reserved for 170 system us
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H8S/2456, H8S/2456R, H8S/2454 Group Section 5 Interrupt Controller 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by INTCR. Table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2. Table 5.
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H8S/2456, H8S/2456R, H8S/2454 Group 5.6.1 Section 5 Interrupt Controller Interrupt Control Mode 0 In interrupt control mode 0, interrupt requests except for NMI are masked by the I bit of CCR in the CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 5 Interrupt Controller Program execution status No Interrupt generated? Yes Yes NMI No I=0 No Hold pending Yes IRQ0 Yes No IRQ1 Yes No SSTXI Yes Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Page 140 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group 5.6.2 Section 5 Interrupt Controller Interrupt Control Mode 2 In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting. Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case. 1.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 5 Interrupt Controller Program execution status Interrupt generated? No Yes Yes NMI No Level 7 interrupt? No Yes Mask level 6 or below? Yes Level 6 interrupt? No No Yes Mask level 5 or below? Level 1 interrupt? No Yes No Yes Mask level 0? No Yes Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.
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H8S/2456, H8S/2456R, H8S/2454 Group 5.6.3 Section 5 Interrupt Controller Interrupt Exception Handling Sequence Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. R01UH0309EJ0500 Rev. 5.
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Page 144 of 1408 (1) (2) (4) (3) Internal operation Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.
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H8S/2456, H8S/2456R, H8S/2454 Group 5.6.4 Section 5 Interrupt Controller Interrupt Response Times Table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.4 are explained in table 5.5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 5 Interrupt Controller Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device 8 Bit Bus 16 Bit Bus Symbol Internal Memory 2-State Access 3-State Access 2-State Access 3-State Access Instruction fetch SI 1 4 6+2m 2 3+m Branch address read SJ Stack manipulation SK [Legend] m: Number of wait states in an external device access. 5.6.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 5 Interrupt Controller 5.7 Usage Notes 5.7.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to mask interrupts, the masking becomes effective after execution of the instruction.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 5 Interrupt Controller 5.7.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.7.
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H8S/2456, H8S/2456R, H8S/2454 Group 5.7.6 Section 5 Interrupt Controller IRQ Status Register (ISR) Depending on the pin status following a reset, IRQnF may be set to 1. Therefore, always read ISR and clear it to 0 after resets. R01UH0309EJ0500 Rev. 5.
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Section 5 Interrupt Controller Page 150 of 1408 H8S/2456, H8S/2456R, H8S/2454 Group R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the bus mastership⎯the CPU, DMA controller (DMAC), EXDMA controller (EXDMAC)*, and data transfer controller (DTC). A block diagram of the bus controller is shown in figure 6.1.
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Section 6 Bus Controller (BSC) H8S/2456, H8S/2456R, H8S/2454 Group • Idle cycle insertion Idle cycles can be inserted between external read cycles to different areas Idle cycles can be inserted before the write cycle after a read cycle Idle cycles can be inserted before the read cycle after a write cycle • Write buffer function External write cycles and internal accesses can be executed in parallel DMAC single address transfers and internal accesses can be executed in parallel • Bus arbitration function I
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H8S/2456, H8S/2456R, H8S/2454 Group EXDMAC address bus Internal address bus Section 6 Bus Controller (BSC) Address selector CS7 to CS0 Area decoder WAIT BREQ BACK BREQO External bus controller Internal bus master bus request signal EXDMAC bus request signal* Internal bus master bus acknowledge signal EXDMAC bus acknowledge signal* External bus arbiter External bus control signals Internal bus control signals Internal bus controller CPU bus request signal DTC bus request signal DMAC bus request si
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) 6.2 Input/Output Pins Table 6.1 shows the pin configuration of the bus controller. Table 6.1 Pin Configuration Name Symbol I/O Function Address strobe AS Output Strobe signal indicating that normal space is accessed and address output on address bus is enabled. Address hold AH Output Signal indicating the timing for latching the address when the address/data multiplexed I/O space is set.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Name Symbol I/O Function Chip select 4/ row address strobe 4/ 1 write enable* CS4/ RAS4/ WE*1 Output Strobe signal indicating that area 4 is selected, DRAM row address strobe signal when area 4 is DRAM space, or write enable signal of the synchronous DRAM when the synchronous DRAM interface is selected.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Name Symbol I/O Function Data transfer acknowledge 1 (DMAC) DACK1 Output Data transfer acknowledge signal for single address transfer by DMAC channel 1. Data transfer acknowledge 0 (DMAC) DACK0 DACK0 Data transfer acknowledge signal for single address transfer by DMAC channel 0. Data transfer acknowledge 3*2 EDACK3*2 Output (EXDMAC) Data transfer acknowledge signal for single address transfer by EXDMAC channel 3.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.3 Section 6 Bus Controller (BSC) Register Descriptions The bus controller has the following registers.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) 6.3.1 Bus Width Control Register (ABWCR) ABWCR designates each area in the external address space as either 8-bit access space or 16-bit access space. Bit Bit Name Initial Value* R/W Description 7 ABW7 1/0 R/W Area 7 to 0 Bus Width Control 6 ABW6 1/0 R/W 5 ABW5 1/0 R/W 4 ABW4 1/0 R/W These bits select whether the corresponding area is to be designated as 8-bit access space or 16-bit access space.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.3.3 Section 6 Bus Controller (BSC) Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH, and WTCRBL) WTCRA and WTCRB select the number of program wait states for each area in the external address space. In addition, CAS latency is set when a synchronous DRAM* is connected. Note: * The synchronous DRAM interface is not supported by the H8S/2456 Group and H8S/2454 Group.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 10 W62 1 R/W Area 6 Wait Control 2 to 0 9 W61 1 R/W 8 W60 1 R/W These bits select the number of program wait states when accessing area 6 while AST6 bit in ASTCR = 1.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) • WTCRAL Bit Bit Name Initial Value R/W Description 7 ⎯ 0 R Reserved This bit is always read as 0 and cannot be modified. 6 W52 1 R/W Area 5 Wait Control 2 to 0 5 W51 1 R/W 4 W50 1 R/W These bits select the number of program wait states when accessing area 5 while AST5 bit in ASTCR = 1.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) • WTCRBH Bit Bit Name Initial Value R/W Description 15 ⎯ 0 R Reserved This bit is always read as 0 and cannot be modified. 14 W32 1 R/W Area 3 Wait Control 2 to 0 13 W31 1 R/W 12 W30 1 R/W These bits select the number of program wait states when accessing area 3 while AST3 bit in ASTCR = 1.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 10 W22 1 R/W Area 2 Wait Control 2 to 0 9 W21 1 R/W 8 W20 1 R/W These bits select the number of program wait states when accessing area 2 while AST2 bit in ASTCR = 1. A CAS latency is set when the synchronous DRAM* is connected. The setting of area 2 is reflected to the setting of areas 2 to 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) • WTCRBL Bit Bit Name Initial Value R/W Description 7 ⎯ 0 R Reserved This bit is always read as 0 and cannot be modified. 6 W12 1 R/W Area 1 Wait Control 2 to 0 5 W11 1 R/W 4 W10 1 R/W These bits select the number of program wait states when accessing area 1 while AST1 bit in ASTCR = 1.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.3.4 Section 6 Bus Controller (BSC) Read Strobe Timing Control Register (RDNCR) RDNCR selects the read strobe signal (RD) negation timing in a basic bus interface read access. Bit Bit Name Initial Value R/W Description 7 6 5 4 3 2 1 0 RDN7 RDN6 RDN5 RDN4 RDN3 RDN2 RDN1 RDN0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read Strobe Timing Control 7 to 0 These bits set the negation timing of the read strobe in a corresponding area read access.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 φ RD RDNn = 0 Data RD RDNn = 1 Data Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space) Page 166 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.3.5 Section 6 Bus Controller (BSC) CS Assertion Period Control Registers H, L (CSACRH, CSACRL) CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip select signals (CSn) and address signals is to be extended. Extending the assertion period of the CSn and address signals allows flexible interfacing to external I/O devices.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Bus cycle Th T1 T2 T3 Tt φ Address CS RD Read Data HWR, LWR Write Data Figure 6.3 CS and Address Assertion Period Extension (Example of 3-State Access Space and RDNn = 0) Page 168 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.3.6 Section 6 Bus Controller (BSC) Area 0 Burst ROM Interface Control Register (BROMCRH) Area 1 Burst ROM Interface Control Register (BROMCRL) BROMCRH and BROMCRL are used to make burst ROM interface settings. Area 0 and area 1 burst ROM interface settings can be made independently in BROMCRH and BROMCRL, respectively. Bit Bit Name Initial Value R/W Description 7 BSRMn 0 R/W Burst ROM Interface Select Selects the basic bus interface or burst ROM interface.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) 6.3.7 Bus Control Register (BCR) BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of WAIT pin input. Bit Bit Name Initial Value R/W 15 BRLE 0 R/W Description External Bus Release Enable Enables or disables external bus release.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 10 ICIS0 1 R/W Idle Cycle Insert 0 When an external read cycle and external write cycle are performed consecutively, an idle cycle can be inserted between the bus cycles. 0: Idle cycle not inserted 1: Idle cycle inserted 9 WDBE 0 R/W Write Data Buffer Enable The write data buffer function can be used for an external write cycle or DMAC single address transfer cycle.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) 6.3.8 Address/Data Multiplexed I/O Control Register (MPXCR) MPXCR is used to make address/data multiplexed I/O interface settings. Bit Bit Name Initial Value R/W Description 7 MPXE 0 R/W Address/Data Multiplexed I/O Interface Enable These bits select the bus interface for areas 6 and 7. 0: Basic bus interface 1: Address/data multiplexed I/O interface 6 to 1 ⎯ All 0 R/W Reserved These bits can be read from or written to.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.3.9 Section 6 Bus Controller (BSC) DRAM Control Register (DRAMCR) DRAMCR is used to make DRAM/synchronous DRAM interface settings. Note: The synchronous DRAM interface is not supported by the H8S/2456 Group and H8S/2454 Group. Bit Bit Name Initial Value R/W Description 15 OEE 0 R/W OE Output Enable The OE signal used when EDO page mode DRAM is connected can be output. The OE signal is common to all areas designated as DRAM space.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 12 CAST 0 R/W Column Address Output Cycle Number Select Selects whether the column address output cycle in DRAM access comprises 3 states or 2 states. The setting of this bit applies to all areas designated as DRAM space. 0: Column address output cycle comprises 2 states 1: Column address output cycle comprises 3 states 11 ⎯ 0 R/W Reserved This bit can be read from or written to.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 10 RMTS2 0 R/W 9 RMTS1 0 R/W DRAM/Continuous Synchronous DRAM Space Select 8 RMTS0 0 R/W These bits designate DRAM/continuous synchronous DRAM space for areas 2 to 5. When continuous DRAM space is set, it is possible to connect large-capacity DRAM exceeding 2 Mbytes per area. In this case, the RAS signal is output from the CS2 pin.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 6 RCDM 0 R/W RAS Down Mode When access to DRAM space is interrupted by an access to normal space, an access to an internal I/O register, etc., this bit selects whether the RAS signal is held low while waiting for the next DRAM access (RAS down mode), or is driven high again (RAS up mode). The setting of this bit is valid only when the BE bit is set to 1.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 4 EDDS 0 R/W EXDMAC Single Address Transfer Option Selects whether full access is always performed or burst access is enabled when EXDMAC single address transfer is performed on the DRAM/synchronous DRAM.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 2 MXC2 0 R/W Address Multiplex Select 1 MXC1 0 R/W 0 MXC0 0 R/W These bits select the size of the shift toward the lower half of the row address in row address/column address multiplexing. In burst operation on the DRAM/synchronous DRAM interface, these bits also select the row address bits to be used for comparison.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 2 MXC2 0 R/W 011: 11-bit shift 1 MXC1 0 R/W • 0 MXC0 0 R/W When 8-bit access space is designated: Row address bits A23 to A11 used for comparison When 16-bit access space is designated: Row address bits A23 to A12 used for comparison Synchronous DRAM interface 100: 8-bit shift • When 8-bit access space is designated: Row address bits A23 to A8 used for comparison • When 16-b
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 2 MXC2 0 R/W 111: 11-bit shift 1 MXC1 0 R/W • 0 MXC0 0 R/W When 8-bit access space is designated: Row address bits A23 to A11 used for comparison • When 16-bit access space is designated: Row address bits A23 to A12 used for comparison The precharge-sel is A15 to A12 of the column address.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.3.10 Section 6 Bus Controller (BSC) DRAM Access Control Register (DRACCR) DRACCR is used to set the DRAM/synchronous DRAM interface bus specifications. Note: The synchronous DRAM interface is not supported by the H8S/2456 Group and H8S/2454 Group.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 10 ⎯ 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. 9 RCD1 0 R/W RAS-CAS Wait Control 8 RCD0 0 R/W These bits select a wait cycle to be inserted between the RAS assert cycle and CAS assert cycle. A 1- to 4-state wait cycle can be inserted.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl Tc2 φ SDRAMφ Address bus Column address Precharge-sel Column address Row address Row address RAS SDWCD 0 CAS WE CKE High DQMU, DQML Data bus Address bus PALL ACTV NOP WRIT Tp Tr Tc1 Tc2 Column address Precharge-sel Row address NOP Column address Row address RAS SDWCD 1 CAS WE CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT Figure 6.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) 6.3.11 Refresh Control Register (REFCR) REFCR specifies DRAM/synchronous DRAM interface refresh control. Note: The synchronous DRAM interface is not supported by the H8S/2456 Group and H8S/2454 Group. Bit Bit Name Initial Value R/W Description 15 CMF 0 R/(W)* Compare Match Flag Status flag that indicates a match between the values of RTCNT and RTCOR.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 11 ⎯ 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. 10 RTCK2 0 R/W Refresh Counter Clock Select 9 RTCK1 0 R/W 8 RTCK0 0 R/W These bits select the clock to be used to increment the refresh counter. When the input clock is selected with bits RTCK2 to RTCK0, the refresh counter begins counting up.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 5 RLW1 0 R/W Refresh Cycle Wait Control 4 RLW0 0 R/W These bits select the number of wait states to be inserted in a DRAM interface CAS-before-RAS refresh cycle/synchronous DRAM interface autorefresh cycle. This setting applies to all areas designated as DRAM/continuous synchronous DRAM space.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.3.12 Section 6 Bus Controller (BSC) Refresh Timer Counter (RTCNT) RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits RTCK2 to RTCK0 in REFCR. When RTCNT matches RTCOR (compare match), the CMF flag in REFCR is set to 1 and RTCNT is cleared to H'00. If the RFSHE bit in REFCR is set to 1 at this time, a refresh cycle is started.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) 6.4 Bus Control 6.4.1 Area Division The bus controller divides the 16-Mbyte address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external address space in area units. Chip select signals (CS0 to CS7) can be output for each area. In normal mode, a part of area 0, 64-Kbyte address space, is controlled. Figure 6.6 shows an outline of the memory map.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.4.2 Section 6 Bus Controller (BSC) Bus Specifications The external address space bus specifications consist of five elements: bus width, number of access states, number of program wait states, read strobe timing, and chip select (CS) assertion period extension states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Table 6.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.4.
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Section 6 Bus Controller (BSC) (3) H8S/2456, H8S/2456R, H8S/2454 Group Areas 2 to 5 In externally expanded mode, areas 2 to 5 are all external address space. When area 2 to 5 external space is accessed, signals CS2 to CS5 can be output. The basic bus interface, DRAM interface, or synchronous DRAM interface can be selected for the memory interface of areas 2 to 5. With the DRAM interface, signals CS2 and CS5 are used as RAS signals.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.4.4 Section 6 Bus Controller (BSC) Chip Select Signals This LSI can output chip select signals (CS0 to CS7) for areas 0 to 7. The signal outputs low when the corresponding external space area is accessed. Figure 6.7 shows an example of CS0 to CS7 signals output timing. Enabling or disabling of CS0 to CS7 signals output is set by the data direction register (DDR) bit for the port corresponding to the CS0 to CS7 pins.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) 6.5 Basic Bus Interface The basic bus interface enables direct connection of ROM, SRAM, and so on. 6.5.1 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword.
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H8S/2456, H8S/2456R, H8S/2454 Group (2) Section 6 Bus Controller (BSC) 16-Bit Access Space Figure 6.9 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword access is executed as two word accesses.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) 6.5.2 Valid Strobes Table 6.3 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid for both the upper and the lower half of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.5.3 (1) Section 6 Bus Controller (BSC) Basic Timing 8-Bit, 2-State Access Space Figure 6.10 shows the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is always fixed high. Wait states can be inserted. Bus cycle T2 T1 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Notes: 1.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) (2) 8-Bit, 3-State Access Space Figure 6.11 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is always fixed high. Wait states can be inserted. Bus cycle T1 T3 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR High LWR Write D15 to D8 D7 to D0 Valid High impedance Notes: 1. n = 0 to 7 2.
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H8S/2456, H8S/2456R, H8S/2454 Group (3) Section 6 Bus Controller (BSC) 16-Bit, 2-State Access Space Figures 6.12 to 6.14 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the lower half (D7 to D0) for odd addresses. Wait states cannot be inserted.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Bus cycle T2 T1 φ Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 D7 to D0 High impedance Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access) Page 200 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.14 Bus Timing for 16-Bit, 2-State Access Space (Word Access) R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) (4) 16-Bit, 3-State Access Space Figures 6.15 to 6.17 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the lower half (D7 to D0) for odd addresses. Wait states can be inserted.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 D7 to D0 High impedance Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access) R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.17 Bus Timing for 16-Bit, 3-State Access Space (Word Access) Page 204 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.5.4 Section 6 Bus Controller (BSC) Wait Control When accessing external space, this LSI can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) By program wait T1 T2 Tw By WAIT pin Tw Tw T3 φ WAIT Address bus AS RD Read Data bus Read data HWR, LWR Write Data bus Write data Notes: 1. Downward arrows indicate the timing of WAIT pin sampling. 2. When RDNn = 0 Figure 6.18 Example of Wait State Insertion Timing 6.5.5 Read Strobe (RD) Timing The read strobe (RD) timing can be changed for individual areas by setting bits RDN7 to RDN0 to 1 in RDNCR. Figure 6.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 φ Address bus CSn AS RD RDNn = 0 Data bus RD RDNn = 1 Data bus DACK, EDACK Figure 6.19 Example of Read Strobe Timing R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) 6.5.6 Extension of Chip Select (CS) Assertion Period Some external I/O devices require a setup time and hold time between address and CS signals and strobe signals such as RD, HWR, and LWR. Settings can be made in the CSACR register to insert states in which only the CS, AS, and address signals are asserted before and after a basic bus space access cycle. Extension of the CS assertion period can be set for individual areas.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Both extension state Th inserted before the basic bus cycle and extension state Tt inserted after the basic bus cycle, or only one of these, can be specified for individual areas. Insertion or noninsertion can be specified for the Th state with the upper 8 bits (CSXH7 to CSXH0) in the CSACR register, and for the Tt state with the lower 8 bits (CSXT7 to CSXT0). 6.
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Section 6 Bus Controller (BSC) 6.6.3 H8S/2456, H8S/2456R, H8S/2454 Group Data Bus The bus width of the address/data multiplexed I/O space can be specified for either 8-bit access space or 16-bit access space by the ABW7 and ABW6 bits in ABWCRA. For the 8-bit access space, AD15 to AD8 are valid for both address and data. For the 16-bit access space, AD15 to AD0 are valid for both address and data.
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H8S/2456, H8S/2456R, H8S/2454 Group (1) Section 6 Bus Controller (BSC) 8-Bit, 2-State Data Access Space Figure 6.21 shows the bus timing for an 8-bit, 2-state data access space. When an 8-bit access space is accessed, the upper halves (AD15 to AD8) of both the address bus and data bus are used. Wait states cannot be inserted in the data cycle.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) (2) 8-Bit, 3-State Data Access Space Figure 6.22 shows the bus timing for an 8-bit, 3-state data access space. When an 8-bit access space is accessed, the upper halves (AD15 to AD8) of both the address bus and data bus are used. Wait states can be inserted in the data cycle.
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H8S/2456, H8S/2456R, H8S/2454 Group (3) Section 6 Bus Controller (BSC) 16-Bit, 2-State Data Access Space Figures 6.23 to 6.25 show bus timings for a 16-bit, 2-state data access space. When a 16-bit access space is accessed, the entire address bus (AD15 to AD0) is used for all addresses, and the upper half (AD15 to AD0) of the data bus is used for even addresses and the lower half (AD7 to AD0) of the data bus is used for odd addresses. Wait states cannot be inserted in the data cycle.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Address cycle Tma1 Tma2 Data cycle T1 T2 φ Address bus CSn AH RD Read AD15 to AD8 Address AD7 to AD0 Address Read data HWR LWR Write AD15 to AD8 Address AD7 to AD0 Address Write data Notes: 1. n = 6, 7 2. When RDNn = 0 Figure 6.24 Bus Timing for 16-Bit, 2-State Data Access Space (Odd Address Byte Access) Page 214 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Address cycle Tma1 Tma2 Data cycle T1 T2 φ Address bus CSn AH RD Read AD15 to AD8 Address Read data AD7 to AD0 Address Read data HWR LWR Write AD15 to AD8 Address Write data AD7 to AD0 Address Write data Notes: 1. n = 6, 7 2. When RDNn = 0 Figure 6.25 Bus Timing for 16-Bit, 2-State Data Access Space (Word Access) R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) (4) 16-Bit, 3-State Data Access Space Figures 6.26 to 6.28 show bus timings for a 16-bit, 3-state data access space. When a 16-bit access space is accessed, the entire address bus (AD15 to AD0) is used for all addresses, and the upper half (AD15 to AD8) of the data bus is used for even addresses and the lower half (AD7 to AD0) of the data bus is used for odd addresses. Wait states can be inserted in the data cycle.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Address cycle Tma1 Tma2 Data cycle T1 T2 T3 φ Address bus CSn AH RD Read AD15 to AD8 Address AD7 to AD0 Address Read data HWR LWR Write AD15 to AD8 Address AD7 to AD0 Address Write data Notes: 1. n = 6, 7 2. When RDNn = 1 Figure 6.27 Bus Timing for 16-Bit, 3-State Data Access Space (Odd Address Byte Access) R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Address cycle Tma1 Tma2 Data cycle T1 T2 T3 φ Address bus CSn AH RD Read AD15 to AD8 Address Read data AD7 to AD0 Address Read data HWR LWR Write AD15 to AD8 Address Write data AD7 to AD0 Address Write data Notes: 1. n = 6, 7 2. When RDNn = 1 Figure 6.28 Bus Timing for 16-Bit, 3-State Data Access Space (Word Access) Page 218 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.6.6 (1) Section 6 Bus Controller (BSC) Wait Control Address Cycle A single address wait cycle Tmaw can be inserted between Tma1 and Tma2 cycles by setting the ADDEX bit in MPXCR to 1. Figure 6.29 shows the access timing when the address cycle is three cycles.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) (2) Data Cycle In the data cycle, program wait insertion and pin wait insertion by the WAIT pin are enabled in the same way as in the basic bus interface. For details, refer to section 6.5.4, Wait Control. Wait control settings do not affect the address cycles. 6.6.7 Read Strobe (RD) Timing In the address/data multiplexed I/O interface, the read strobe timing of data cycles can be modified in the same way as in the basic bus interface.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.6.8 Section 6 Bus Controller (BSC) Extension of Chip Select (CS) Assertion Period in Data Cycle In the address/data multiplexed I/O interface, extension cycles can be inserted before and after the data cycle. For details, see section 6.5.6, Extension of Chip Select (CS) Assertion Period. Figure 6.31 shows an example of the timing when the chip select assertion period is extended in the data cycle.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) When consecutively reading from the same area connected to a peripheral LSI whose output floating time is long, data outputs from the peripheral LSI may conflict with address outputs from this LSI. The data conflict can be avoided by inserting the CS assertion period extension cycle after the access cycle. Figure 6.32 shows an example of the operation.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.7 Section 6 Bus Controller (BSC) DRAM Interface In this LSI, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing performed. The DRAM interface allows DRAM to be directly connected to this LSI. A DRAM space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Burst operation is also possible, using fast page mode. 6.7.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) 6.7.2 Address Multiplexing With DRAM space, the row address and column address are multiplexed. In address multiplexing, the size of the shift of the row address is selected with bits MXC2 to MXC0 in DRAMCR. Table 6.6 shows the relation between the settings of MXC2 to MXC0 and the shift size. The MXC2 bit should be cleared to 0 when the DRAM interface is used. Table 6.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.7.3 Section 6 Bus Controller (BSC) Data Bus If a bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM space. In 16-bit DRAM space, ×16-bit configuration DRAM can be connected directly.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) 6.7.4 Pins Used for DRAM Interface Table 6.7 shows the pins used for DRAM interfacing and their functions. Table 6.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.7.5 Section 6 Bus Controller (BSC) Basic Timing Figure 6.33 shows the basic access timing for DRAM space. The four states of the basic timing consist of one Tp (precharge cycle) state, one Tr (row address output cycle) state, and the Tc1 and two Tc2 (column address output cycle) states.
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Section 6 Bus Controller (BSC) H8S/2456, H8S/2456R, H8S/2454 Group When DRAM space is accessed, the RD signal is output as the OE signal for DRAM. When connecting DRAM provided with an EDO page mode, the OE signal should be connected to the (OE) pin of the DRAM. Setting the OEE bit to 1 in DRAMCR enables the OE signal for DRAM space to be output from a dedicated OE pin.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.7.6 Section 6 Bus Controller (BSC) Column Address Output Cycle Control The column address output cycle can be changed from 2 states to 3 states by setting the CAST bit to 1 in DRAMCR. Use the setting that gives the optimum specification values (CAS pulse width, etc.) according to the DRAM connected and the operating frequency of this LSI. Figure 6.34 shows an example of the timing when a 3-state column address output cycle is selected.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) 6.7.7 Row Address Output State Control If the RAST bit is set to 1 in DRAMCR, the RAS signal goes low from the beginning of the Tr state, and the row address hold time and DRAM read access time are changed relative to the fall of the RAS signal. Use the optimum setting according to the DRAM connected and the operating frequency of this LSI. Figure 6.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) If a row address hold time or read access time is necessary, making a setting in bits RCD1 and RCD0 in DRACCR allows from one to three Trw states, in which row address output is maintained, to be inserted between the Tr cycle, in which the RAS signal goes low, and the Tc1 cycle, in which the column address is output.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) 6.7.8 Precharge State Control When DRAM is accessed, a RAS precharge time must be secured. With this LSI, one Tp state is always inserted when DRAM space is accessed. From one to four Tp states can be selected by setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of Tp cycles according to the DRAM connected and the operating frequency of this LSI. Figure 6.37 shows the timing when two Tp states are inserted.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.7.9 Section 6 Bus Controller (BSC) Wait Control There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and pin wait insertion using the WAIT pin. Wait states are inserted to extend the CAS assertion period in a read access to DRAM space, and to extend the write data setup time relative to the falling edge of CAS in a write access.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) By program wait Tp Tr Tc1 Tw By WAIT pin Tw Tc2 φ WAIT Address bus Row address Column address RASn (CSn) UCAS, LCAS Read WE (HWR) High OE (RD) Data bus UCAS, LCAS Write WE (HWR) OE (RD) High Data bus Note: Downward arrows indicate the timing of WAIT pin sampling. n = 2 to 5 Figure 6.38 Example of Wait State Insertion Timing (2-State Column Address Output) Page 234 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Tp Section 6 Bus Controller (BSC) Tr By program wait By WAIT pin Tc1 Tw Tw Tc2 Tc3 φ WAIT Address bus Row address Column address RASn (CSn) UCAS, LCAS Read WE (HWR) High OE (RD) Data bus UCAS, LCAS Write WE (HWR) OE (RD) High Data bus Note: Downward arrows indicate the timing of WAIT pin sampling. n = 2 to 5 Figure 6.39 Example of Wait State Insertion Timing (3-State Column Address Output) R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) 6.7.10 Byte Access Control When DRAM with a ×16-bit configuration is connected, the 2-CAS access method is used for the control signals needed for byte access. Figure 6.40 shows the control timing for 2-CAS access, and figure 6.41 shows an example of 2-CAS DRAM connection.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) 2-CAS type 16-Mbit DRAM 1-Mbyte × 16-bit configuration 10-bit column address This LSI (Address shift size set to 10 bits) RASn (CSn) RAS UCAS UCAS LCAS LCAS HWR (WE) RD (OE) A10 WE OE A9 A9 A8 A8 A7 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 D15 to D0 Row address input: A9 to A0 Column address input: A9 to A0 D15 to D0 Figure 6.41 Example of 2-CAS DRAM Connection R01UH0309EJ0500 Rev. 5.
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Section 6 Bus Controller (BSC) 6.7.11 H8S/2456, H8S/2456R, H8S/2454 Group Burst Operation With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making consecutive accesses to the same row address. This mode enables fast (burst) access of data by simply changing the column address after the row address has been output.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Tp Tr Tc1 Tc2 Tc1 Tc2 φ Address bus Row address Column address 1 Column address 2 RASn (CSn) UCAS, LCAS WE (HWR) Read High OE (RD) Data bus WE (HWR) Write High OE (RD) Data bus Note: n = 2 to 5 Figure 6.42 Operation Timing in Fast Page Mode (RAST = 0, CAST = 0) R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Tp Tr Tc1 Tc2 Tc3 Tc1 Tc2 Tc3 φ Address bus Row address Column address 1 Column address 2 RASn (CSn) UCAS, LCAS WE (HWR) Read High OE (RD) Data bus WE (HWR) Write OE (RD) High Data bus Note: n = 2 to 5 Figure 6.43 Operation Timing in Fast Page Mode (RAST = 0, CAST = 1) The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion method and timing are the same as for full access.
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H8S/2456, H8S/2456R, H8S/2454 Group (2) Section 6 Bus Controller (BSC) RAS Down Mode and RAS Up Mode Even when burst operation is selected, it may happen that access to DRAM space is not continuous, but is interrupted by access to another space. In this case, if the RAS signal is held low during the access to the other space, burst operation can be resumed when the same row address in DRAM space is accessed again.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) DRAM space read Tp Tr Tc1 Tc2 Normal space read DRAM space read T1 Tc1 T2 Tc2 φ Row address Address bus Column address 1 External address Column address 2 RASn (CSn) UCAS, LCAS RD OE Data bus Note: n = 2 to 5 Figure 6.44 Example of Operation Timing in RAS Down Mode (RAST = 0, CAST = 0) Page 242 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) • RAS Up Mode To select RAS up mode, clear the RCDM bit to 0 in DRAMCR. Each time access to DRAM space is interrupted and another space is accessed, the RAS signal goes high again. Burst operation is only performed if DRAM space is continuous. Figure 6.45 shows an example of the timing in RAS up mode.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) 6.7.12 Refresh Control This LSI is provided with a DRAM refresh control function. CAS-before-RAS (CBR) refreshing is used. In addition, self-refreshing can be executed when the chip enters the software standby state. Refresh control is enabled when any area is designated as DRAM space in accordance with the setting of bits RMTS2 to RMTS0 in DRAMCR.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) φ RTCNT N H'00 RTCOR N Refresh request signal and CMF bit setting signal Figure 6.47 Compare Match Timing TRp TRr TRc1 TRc2 φ CSn (RASn) UCAS, LCAS Figure 6.48 CBR Refresh Timing R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) A setting can be made in bits RCW1 and RCW0 in REFCR to delay RAS signal output by one to three cycles. Use bits RLW1 and RLW0 in REFCR to adjust the width of the RAS signal. The settings of bits RCW1, RCW0, RLW1, and RLW0 are valid only in refresh operations. Figure 6.49 shows the timing when bits RCW1 and RCW0 are set. TRp TRrw TRr TRc1 TRc2 φ CSn (RASn) UCAS, CAS Figure 6.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Normal space access request φ A23 to A0 CS AS RD HWR (WE) Refresh period RAS CAS Figure 6.50 Example of CBR Refresh Timing (CBRM = 1) R01UH0309EJ0500 Rev. 5.
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Section 6 Bus Controller (BSC) (2) H8S/2456, H8S/2456R, H8S/2454 Group Self-Refreshing A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM. To select self-refreshing, set the RFSHE bit and SLFRF bit to 1 in REFCR. When a SLEEP instruction is executed to enter software standby mode, the CAS and RAS signals are output and DRAM enters self-refresh mode, as shown in figure 6.51.
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H8S/2456, H8S/2456R, H8S/2454 Group TRp Section 6 Bus Controller (BSC) Software standby TRr TRc3 φ CSn (RASn) UCAS, LCAS HWR (WE) High Note: n = 2 to 5 Figure 6.51 Self-Refresh Timing In some DRAMs provided with a self-refresh mode, the RAS signal precharge time immediately after self-refreshing is longer than the normal precharge time.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Software standby DRAM space write TRc3 TRp1 TRp2 Tp Tr Tc1 Tc2 φ Address bus RASn (CSn) UCAS, LCAS OE (RD) WE (HWR) Data bus Note: n = 2 to 5 Figure 6.52 Example of Timing when Precharge Time after Self-Refreshing Is Extended by 2 States Page 250 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group (3) Section 6 Bus Controller (BSC) Refreshing and All-Module-Clocks-Stopped Mode In this LSI, if the ACSE bit is set to 1 in MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR = H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE, EXMSTPCR = H'FFFF), and a transition is made to the sleep state, the all-module-clocks-stopped mode is entered, in which the bus
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Section 6 Bus Controller (BSC) 6.7.13 H8S/2456, H8S/2456R, H8S/2454 Group DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface When burst mode is selected on the DRAM interface, the DACK and EDACK output timing can be selected with the DDS and EDDS bits in DRAMCR. When DRAM space is accessed in DMAC or EXDMAC single address mode at the same time, these bits select whether or not burst access is to be performed.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Tp Tr Tc1 Tc2 φ Address bus Row address Column address RASn (CSn) UCAS, LCAS WE (HWR) Read High OE (RD) Data bus WE (HWR) Write OE (RD) High Data bus DACK or EDACK Note: n = 2 to 5 Figure 6.53 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1 (RAST = 0, CAST = 0) R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) (2) When DDS = 0 or EDDS = 0 When DRAM space is accessed in DMAC or EXDMAC single address transfer mode, full access (normal access) is always performed. With the DRAM interface, the DACK or EDACK output goes low from the Tr state. In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used when accessing DRAM space. Figure 6.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.8 Section 6 Bus Controller (BSC) Synchronous DRAM Interface In the H8S/2456R Group, external address space areas 2 to 5 can be designated as continuous synchronous DRAM space, and synchronous DRAM interfacing performed. The synchronous DRAM interface allows synchronous DRAM to be directly connected to this LSI. A synchronous DRAM space of up to 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Synchronous DRAM of CAS latency 1 to 4 can be connected.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Commands that are supported by this LSI are NOP, auto-refresh (REF), self-refresh (SELF), all bank precharge (PALL), row address strobe bank-active (ACTV), read (READ), write (WRIT), and mode-register write (MRS). Commands for bank control cannot be used. 6.8.2 Address Multiplexing With continuous synchronous DRAM space, the row address and column address are multiplexed.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.8.3 Section 6 Bus Controller (BSC) Data Bus If the ABW2 bit in ABWCR corresponding to an area designated as continuous synchronous DRAM space is set to 1, areas 2 to 5 are designated as 8-bit continuous synchronous DRAM space; if the bit is cleared to 0, the areas are designated as 16-bit continuous synchronous DRAM space. In 16-bit continuous synchronous DRAM space, ×16-bit configuration synchronous DRAM can be connected directly.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Table 6.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.8.5 Section 6 Bus Controller (BSC) Synchronous DRAM Clock The synchronous clock (SDRAMφ) is output from the CS5 pin. SDRAMφ is shifted by 90° phase from φ. Therefore, a stable margin is ensured for the synchronous DRAM that operates at the rising edge of clocks. Figure 6.55 shows the relationship between φ and SDRAMφ. Tcyc φ 1/4 Tcyc (90°) SDRAMφ Figure 6.55 Relationship between φ and SDRAMφ 6.8.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Tp Tr Column address Row address Tc1 Tc2 φ SDRAMφ Address bus Precharge-sel Column address Row address RAS CAS WE Read CKE High DQMU, DQML Data bus PALL ACTV READ NOP RAS CAS WE Write CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT Figure 6.56 Basic Access Timing of Synchronous DRAM (CAS Latency 1) Page 260 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.8.7 Section 6 Bus Controller (BSC) CAS Latency Control CAS latency is controlled by settings of the W22 to W20 bits of WTCRB. Set the CAS latency count, as shown in table 6.11, by the setting of synchronous DRAM. Depending on the setting, the CAS latency control cycle (Tc1) is inserted. WTCRB can be set regardless of the setting of the AST2 bit of ASTCR. Figure 6.57 shows the CAS latency control timing when synchronous DRAM of CAS latency 3 is connected.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl1 Tcl2 Tc2 φ SDRAMφ Address bus Column address Row address Precharge-sel Row address Column address RAS CAS WE Read CKE High DQMU, DQML Data bus PALL ACTV READ NOP RAS CAS WE Write CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT NOP Figure 6.57 CAS Latency Control Timing (SDWCD = 0, CAS Latency 3) Page 262 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.8.8 Section 6 Bus Controller (BSC) Row Address Output State Control When the command interval specification from the ACTV command to the next READ/WRIT command cannot be satisfied, 1 to 3 states (Trw) that output the NOP command can be inserted between the Tr cycle that outputs the ACTV command and the Tc1 cycle that outputs the column address by setting the RCD1 and RCD0 bits of DRACCR.
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Section 6 Bus Controller (BSC) 6.8.9 H8S/2456, H8S/2456R, H8S/2454 Group Precharge State Count When the interval specification from the PALL command to the next ACTV/REF command cannot be satisfied, from one to four Tp states can be selected by setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of Tp cycles according to the synchronous DRAM connected and the operating frequency of this LSI. Figure 6.59 shows the timing when two Tp states are inserted. Page 264 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) The setting of bits TPC1 and TPC0 is also valid for Tp states in refresh cycles. Tp1 Tp2 Tr Tc1 Tcl Tc2 φ SDRAMφ Address bus Column address Row address Column address Row address Precharge-sel RAS CAS Read WE CKE High DQMU, DQML Data bus PALL NOP ACTV READ NOP RAS CAS Write WE CKE High DQMU, DQML Data bus PALL NOP ACTV NOP WRIT NOP Figure 6.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) 6.8.10 Bus Cycle Control in Write Cycle By setting the SDWCD bit of the DRACCR to 1, the CAS latency control cycle (Tc1) that is inserted by the WTCRB register in the write access of the synchronous DRAM can be disabled. Disabling the CAS latency control cycle can reduce the write-access cycle count as compared to synchronous DRAM read access. Figure 6.60 shows the write access timing when the CAS latency control cycle is disabled.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.8.11 Section 6 Bus Controller (BSC) Byte Access Control When synchronous DRAM with a ×16-bit configuration is connected, DQMU and DQML are used for the control signals needed for byte access. Figures 6.61 and 6.62 show the control timing for DQM, and figure 6.63 shows an example of connection of byte control by DQMU and DQML.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl Tc2 φ SDRAMφ Address bus Column address Row address Precharge-sel Row address Column address RAS CAS WE CKE High DQMU High DQML Upper data bus High impedance Lower data bus PALL ACTV READ NOP Figure 6.62 DQMU and DQML Control Timing (Lower Byte Read Access: CAS Latency 2) Page 268 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) This LSI (Address shift size set to 8 bits) 16-Mbit synchronous DRAM 1 Mword × 16 bits × 4-bank configuration 8-bit column address CS2 (RAS) RAS CS3 (CAS) CAS CS4 (WE) UCAS (DQMU) LCAS (DQML) CS5 (SDRAMφ) WE DQMU DQML CLK A23 A13 (BS1) A21 A12 (BS0) A12 A11 A11 A10 A10 A9 A9 A8 A8 A7 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 D15 to D0 OE (CKE) I/O PORT Row address input: A11 to A0 Column address input:
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Section 6 Bus Controller (BSC) 6.8.12 H8S/2456, H8S/2456R, H8S/2454 Group Burst Operation With synchronous DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, burst access is also provided which can be used when making consecutive accesses to the same row address. This access enables fast access of data by simply changing the column address after the row address has been output.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Tp Tr Column address 1 Row address Tc1 Tcl Tc2 Tc1 Tcl Tc2 φ SDRAMφ Address bus Column address Column address 2 Row address Precharge-sel RAS CAS Read WE CKE High DQMU, DQML Data bus PALL ACTV READ NOP READ NOP RAS CAS Write WE CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT NOP WRIT NOP Figure 6.64 Operation Timing of Burst Access (BE = 1, SDWCD = 0, CAS Latency 2) R01UH0309EJ0500 Rev. 5.
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Section 6 Bus Controller (BSC) (2) H8S/2456, H8S/2456R, H8S/2454 Group RAS Down Mode Even when burst operation is selected, it may happen that access to continuous synchronous DRAM space is not continuous, but is interrupted by access to another space. In this case, if the row address active state is held during the access to the other space, the read or write command can be issued without ACTV command generation similarly to DRAM RAS down mode.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read Tp Tr Tc1 Tcl External space read Tc2 T1 T2 Continuous synchronous DRAM space read Tc1 Tcl Tc2 φ Address bus Column Row address address Precharge-sel Row address Column address External address Column address 2 External address RAS CAS WE CKE High DQMU, DQML Data bus PALL ACTV READ NOP READ NOP Figure 6.
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Section 6 Bus Controller (BSC) 6.8.13 H8S/2456, H8S/2456R, H8S/2454 Group Refresh Control This LSI is provided with a synchronous DRAM refresh control function. Auto refreshing is used. In addition, self-refreshing can be executed when the chip enters the software standby state. Refresh control is enabled when any area is designated as continuous synchronous DRAM space in accordance with the setting of bits RMTS2 to RMTS0 in DRAMCR.
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H8S/2456, H8S/2456R, H8S/2454 Group TRp Section 6 Bus Controller (BSC) TRr TRc1 TRc2 φ SDRAMφ Address bus Precharge-sel RAS CAS WE CKE High PALL REF NOP Figure 6.66 Auto Refresh Timing When the interval specification from the PALL command to the REF command cannot be satisfied, setting the RCW1 and RCW0 bits of REFCR enables one to three wait states to be inserted after the TRp cycle that is set by the TPC1 and TPC0 bits of DRACCR.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) TRp1 TRp2 TRrw TRr TRc1 TRc2 φ SDRAMφ Address bus Precharge-sel RAS CAS WE CKE High PALL NOP REF NOP Figure 6.67 Auto Refresh Timing (TPC = 1, TPC0 = 1, RCW1 = 0, RCW0 = 1) When the interval specification from the REF command to the ACTV cannot be satisfied, setting the RLW1 and RLW0 bits of REFCR enables one to three wait states to be inserted in the refresh cycle.
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H8S/2456, H8S/2456R, H8S/2454 Group TRp Section 6 Bus Controller (BSC) TRr TRr1 TRcw TRc2 φ SDRAMφ Address bus Precharge-sel RAS CAS WE CKE High PALL REF NOP Figure 6.68 Auto Refresh Timing (TPC = 0, TPC0 = 0, RLW1 = 0, RLW0 = 1) R01UH0309EJ0500 Rev. 5.
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Section 6 Bus Controller (BSC) (2) H8S/2456, H8S/2456R, H8S/2454 Group Self-Refreshing A self-refresh mode (battery backup mode) is provided for synchronous DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the synchronous DRAM. To select self-refreshing, set the RFSHE bit to 1 in REFCR. When a SLEEP instruction is executed to enter software standby mode, the SELF command is issued, as shown in figure 6.69.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) TRp TRr PALL SELF Software standby TRc2 φ SDRAMφ Address bus Precharge-sel RAS CAS WE CKE NOP Figure 6.69 Self-Refresh Timing (TPC1 = 1, TPC0 = 0, RCW1 = 0, RCW0 = 0, RLW1 = 0, RLW0 = 0) In some synchronous DRAMs provided with a self-refresh mode, the interval between clearing self-refreshing and the next command is specified.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Continuous synchronous DRAM space write Software standby TRc2 TRp1 TRp2 Tp Tr Column address Row address Tc1 Tcl Tc2 φ SDRAMφ Address bus Precharge-sel Column address Row address RAS CAS WE CKE DQMU, DQML Data bus NOP PALL ACTV NOP NOP NOP Figure 6.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.8.14 Section 6 Bus Controller (BSC) Mode Register Setting of Synchronous DRAM To use synchronous DRAM, mode must be set after power-on. To set mode, set the RMTS2 to RMTS0 bits in DRAMCR to H'5 and enable the synchronous DRAM mode register setting. After that, access the continuous synchronous DRAM space in bytes.
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Section 6 Bus Controller (BSC) 6.8.15 H8S/2456, H8S/2456R, H8S/2454 Group DMAC and EXDMAC Single Address Transfer Mode and Synchronous DRAM Interface When burst mode is selected on the synchronous DRAM interface, the DACK and EDACK output timing can be selected with the DDS and EDDS bits in DRAMCR. When continuous synchronous DRAM space is accessed in DMAC/EXDMAC single address mode at the same time, these bits select whether or not burst access is to be performed.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Tp Tr Column address Row address Tc1 Tcl Tc2 φ SDRAMφ Address bus Precharge-sel Column address Row address RAS CAS WE Read CKE High DQMU, DQML Data bus PALL ACTV READ NOP RAS CAS WE Write CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT NOP DACK or EDACK Figure 6.72 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1 R01UH0309EJ0500 Rev. 5.
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Section 6 Bus Controller (BSC) H8S/2456, H8S/2456R, H8S/2454 Group When DDS = 0 or EDDS = 0: When continuous synchronous DRAM space is accessed in DMAC or EXDMAC single address transfer mode, full access (normal access) is always performed. With the synchronous DRAM interface, the DACK or EDACK output goes low from the Tr state. In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used when accessing continuous synchronous DRAM space. Figure 6.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl Tc2 φ SDRAMφ Address bus Column address Row address Precharge-sel Row address Column address RAS CAS WE Read CKE High DQMU, DQML Data bus PALL ACTV READ NOP RAS CAS WE Write CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT NOP DACK or RDACK Figure 6.73 Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) (2) Read Data Extension If the CKSPE bit is set to 1 in DRACCR when the continuous synchronous DRAM space is readaccessed in DMAC/EXDMAC single address mode, the establishment time for the read data can be extended by clock suspend mode. The number of states for insertion of the read data extension cycle (Tsp) is set in bits RDXC1 and RDXC0 in DRACCR. Be sure to set the OEE bit to 1 in DRAMCR when the read data will be extended.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.9 Section 6 Bus Controller (BSC) Burst ROM Interface In this LSI, external address space areas 0 and 1 can be designated as burst ROM space, and burst ROM interfacing performed. The burst ROM space enables ROM with burst access capability to be accessed at high speed. Areas 1 and 0 can be designated as burst ROM space by means of bits BSRM1 and BSRM0 in BROMCR.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Full access T1 T2 Burst access T3 T1 T2 T1 T2 φ Upper address bus Lower address bus CSn AS RD Data bus Note: n = 1 and 0 Figure 6.75 Example of Burst ROM Access Timing (ASTn = 1, 2-State Burst Cycle) Page 288 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Full access T1 T2 Burst access T1 T1 φ Upper address bus Lower address bus CSn AS RD Data bus Note: n = 1 and 0 Figure 6.76 Example of Burst ROM Access Timing (ASTn = 0, 1-State Burst Cycle) 6.9.2 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) on the burst ROM interface. See section 6.5.4, Wait Control.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) 6.10 Idle Cycle 6.10.1 Operation When this LSI accesses external address space, it can insert an idle cycle (Ti) between bus cycles in the following three cases: (1) when read accesses in different areas occur consecutively, (2) when a write cycle occurs immediately after a read cycle, and (3) when a read cycle occurs immediately after a write cycle. Insertion of a 1-state or 2-state idle cycle can be selected with the IDLC bit in BCR.
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H8S/2456, H8S/2456R, H8S/2454 Group (2) Section 6 Bus Controller (BSC) Write after Read If an external write occurs after an external read while the ICIS0 bit is set to 1 in BCR, an idle cycle is inserted at the start of the write cycle. Figure 6.78 shows an example of the operation in this case. In this example, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) (3) Read after Write If an external read occurs after an external write while the ICIS2 bit is set to 1 in BCR, an idle cycle is inserted at the start of the read cycle. Figure 6.79 shows an example of the operation in this case. In this example, bus cycle A is a CPU write cycle and bus cycle B is a read cycle from an external device.
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H8S/2456, H8S/2456R, H8S/2454 Group (4) Section 6 Bus Controller (BSC) Relationship between Chip Select (CS) Signal and Read (RD) Signal Depending on the system's load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 6.80. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) (5) Idle Cycle in Case of DRAM Space Access after Normal Space Access In a DRAM space access following a normal space access, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads in different areas, for example, if the second read is a full access to DRAM space, only a Tp cycle is inserted, and a Ti cycle is not. The timing in this case is shown in figure 6.81.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) External read DRAM space read Tp Tr Tc1 Tc2 T1 T2 T3 DRAM space read Ti Tc1 Tc2 φ Address bus RD RAS UCAS, LCAS Data bus Idle cycle Figure 6.82 Example of Idle Cycle Operation in RAS Down Mode (Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0) External read DRAM space read Tp Tr Tc1 Tc2 T1 T2 T3 DRAM space write Ti Tc1 Tc2 φ Address bus RD HWR RAS UCAS, LCAS Data bus Idle cycle Figure 6.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) (6) Idle Cycle in Case of Continuous Synchronous DRAM Space Access after Normal Space Access In a continuous synchronous DRAM space access following a normal space access, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads in different areas, for example, if the second read is a full access to continuous synchronous DRAM space, only Tp cycle is inserted, and Ti cycle is not.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid and an idle cycle is inserted. However, in read access, note that the timings of DQMU and DQML differ according to the settings of the IDLC bit. The timing in this case is illustrated in figures 6.85 and 6.86. In write access, DQMU and DQML are not in accordance with the settings of the IDLC bit.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read Tp Tr Tc1 Tcl Continuous synchronous DRAM space read External space read Tc2 T1 T2 T3 Ti Ti Tc1 TCl Tc2 φ Address bus Row Column address address Precharge-sel Row address Column address 1 External address Column address 2 External address RAS CAS WE CKE High DQMU, DQML RD HWR, LWR High Data bus PALL ACTV READ NOP READ NOP Idle cycle Figure 6.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read Tp Tr Tc1 Tcl External space read Tc2 T1 T2 T3 Continuous synchronous DRAM space write Ti Tc1 Tc2 TCl φ Address bus Row Column address address Precharge-sel Row address Column address 1 External address Column address 2 External address RAS CAS WE CKE High DQMU, DQML RD HWR, LWR High Data bus PALL ACTV READ NOP WRIT NOP Idle cycle Figure 6.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) (7) Idle Cycle in Case of Normal Space Access after DRAM Space Access (a) Normal space access after DRAM space read access While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after DRAM space access is disabled. Idle cycle insertion after DRAM space access can be enabled by setting the DRMI bit to 1.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) DRAM space read Tp Tr Tc1 External address space write DRAM space read Tc2 Ti T1 T2 T3 Tc1 Tc2 φ Address bus RD HWR, LWR RAS UCAS, LCAS Data bus Idle cycle Figure 6.89 Example of Idle Cycle Operation after DRAM Access (Write after Read) (IDLC = 0, RAST = 0, CAST = 0) R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) (b) Normal space access after DRAM space write access While the ICIS2 bit is set to 1 in BCR and a normal space read access occurs after DRAM space write access, idle cycle is inserted in the first read cycle. The number of states of the idle cycle to be inserted is in accordance with the setting of the IDLC bit. It does not depend on the DRMI bit in DRACCR. Figure 6.
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H8S/2456, H8S/2456R, H8S/2454 Group (a) Section 6 Bus Controller (BSC) Normal space access after a continuous synchronous DRAM space read access While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after continuous synchronous DRAM space read access is disabled. Idle cycle insertion after continuous synchronous DRAM space read access can be enabled by setting the DRMI bit to 1.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) (b) Normal space access after a continuous synchronous DRAM space write access If a normal space read cycle occurs after a continuous synchronous DRAM space write access while the ICIS2 bit is set to 1 in BCR, idle cycle is inserted at the start of the read cycle. The number of states of the idle cycle to be inserted is in accordance with the setting of bit IDLC. It is not in accordance with the DRMI bit in DRACCR. Figure 6.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Table 6.12 shows whether there is an idle cycle insertion or not in the case of mixed accesses to normal space and DRAM space/continuous synchronous DRAM space. Table 6.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Previous Access Next Access ICIS2 ICIS1 ICIS0 DRMI IDLC Idle cycle Normal space write Normal space read 0 ⎯ ⎯ ⎯ ⎯ Disabled 1 ⎯ ⎯ ⎯ 0 1 state inserted 1 2 states inserted DRAM/continuous synchronous DRAM* DRAM/continuous synchronous DRAM* space read 0 ⎯ ⎯ ⎯ ⎯ Disabled 1 ⎯ ⎯ ⎯ 0 1 state inserted 1 2 states inserted Normal space read 0 ⎯ ⎯ ⎯ ⎯ Disabled 1 ⎯ ⎯ ⎯ 0 1 state inserted 1 2 states
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) DRAM space read φ Tp Tr Tc1 DRAM space write Tc2 Ti Tc1 Tc2 Address bus RASn (CSn) UCAS, LCAS WE (HWR) OE (RD) Data bus Note: n = 2 to 5 Idle cycle Figure 6.93 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and Write Accesses to DRAM Space in RAS Down Mode R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read Tp Tr Tc1 Tcl Continuous synchronous DRAM space write Tc2 Ti Tc1 Tc2 φ Address bus Column Row address address Precharge-sel Row address Column address External address RAS CAS WE CKE High DQMU, DQML Data bus PALL ACTV READ NOP WRIT Idle cycle Figure 6.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.10.2 Section 6 Bus Controller (BSC) Pin States in Idle Cycle Table 6.13 shows the pin states in an idle cycle. Table 6.13 Pin States in Idle Cycle Pins Pin State A23 to A0 Contents of following bus cycle D15 to D0 CSn (n = 7 to 0) High impedance High*1 *2 UCAS, LCAS High*2 AS/AH High RD High OE High HWR, LWR High DACKn (n = 1, 0) High EDACKn (n = 3 to 0) High Notes: 1. Remains low in DRAM space RAS down mode. 2.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) 6.11 Write Data Buffer Function This LSI has a write data buffer function for the external data bus. Using the write data buffer function enables external writes and DMA single address mode transfers to be executed in parallel with internal accesses. The write data buffer function is made available by setting the WDBE bit to 1 in BCR. Figure 6.95 shows an example of the timing when the write data buffer function is used.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.12 Section 6 Bus Controller (BSC) Bus Release This LSI can release the external bus in response to a bus request from an external device. In the external bus released state, internal bus masters except the EXDMAC* continue to operate as long as there is no external access. If any of the following requests are issued in the external bus released state, the BREQO signal can be driven low to output a bus request externally.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) If an external bus release request and external access occur simultaneously, the order of priority is as follows: (High) External bus release > External access by internal bus master (Low) If a refresh request and external bus release request occur simultaneously, the order of priority is as follows: (High) Refresh > External bus release (Low) Note: * Not supported by the H8S/2454 Group. 6.12.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.12.3 Section 6 Bus Controller (BSC) Transition Timing Figure 6.96 shows the timing for transition to the bus released state. External space access cycle CPU cycle External bus released state T1 T2 φ High impedance Address bus High impedance Data bus High impedance AS High impedance RD High impedance HWR, LWR BREQ BACK BREQO [1] [2] [3] [4] [5] [6] [7] [8] [1] Low level of BREQ signal is sampled at rise of φ.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 6 Bus Controller (BSC) External space read T1 CPU cycle External bus released state T2 φ SDRAMφ High impedance Address bus High impedance Data bus Row address Precharge-sel High impedance High impedance RAS High impedance CAS High impedance WE High impedance CKE High impedance DQMU, DQML BREQ BACK BREQO NOP PALL [1] [2] NOP [3] NOP [4] [5] [8] [6] [7] [9] [1] Low level of BREQ signal is sampled at rise of φ. [2] PALL command is issued.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.13 Section 6 Bus Controller (BSC) Bus Arbitration This LSI has a bus arbiter that arbitrates bus mastership operations (bus arbitration). There are four bus masters⎯the CPU, DTC, DMAC, and EXDMAC*⎯that perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal.
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Section 6 Bus Controller (BSC) 6.13.2 H8S/2456, H8S/2456R, H8S/2454 Group Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific timings at which each bus master can relinquish the bus.
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H8S/2456, H8S/2456R, H8S/2454 Group (3) Section 6 Bus Controller (BSC) DMAC The DMAC sends the bus arbiter a request for the bus when an activation request is generated. In the case of an external request in short address mode or normal mode, and in cycle steal mode, the DMAC releases the bus after a single transfer. In block transfer mode, it releases the bus after transfer of one block, and in burst mode, after completion of the transfer.
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Section 6 Bus Controller (BSC) 6.14 H8S/2456, H8S/2456R, H8S/2454 Group Bus Controller Operation in Reset In a reset, this LSI, including the bus controller, enters the reset state immediately, and any executing bus cycle is aborted. 6.15 Usage Notes 6.15.
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H8S/2456, H8S/2456R, H8S/2454 Group 6.15.4 Section 6 Bus Controller (BSC) BREQO Output Timing When the BREQOE bit is set to 1 and the BREQO signal is output, BREQO may go low before the BACK signal. This will occur if the next external access request or CBR refresh request occurs while internal bus arbitration is in progress after the chip samples a low level of BREQ. 6.15.
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Section 6 Bus Controller (BSC) Page 320 of 1408 H8S/2456, H8S/2456R, H8S/2454 Group R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Section 7 DMA Controller (DMAC) This LSI has a built-in DMA controller (DMAC) which can carry out data transfer on up to 4 channels. 7.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) A block diagram of the DMAC is shown in figure 7.1.
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H8S/2456, H8S/2456R, H8S/2454 Group 7.2 Section 7 DMA Controller (DMAC) Input/Output Pins Table 7.1 shows the pin configuration of the interrupt controller. Table 7.
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Section 7 DMA Controller (DMAC) 7.
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H8S/2456, H8S/2456R, H8S/2454 Group Table 7.2 Section 7 DMA Controller (DMAC) Short Address Mode and Full Address Mode (Channel 0) 0 Short address mode specified (channels 0A and 0B operate independently) MAR_0AH MAR_0BH MAR_0AL Specifies transfer source/transfer destination address IOAR_0A Specifies transfer destination/transfer source address ETCR_0A Specifies number of transfers DMACR_0A MAR_0BL Specifies transfer size, mode, activation source.
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Section 7 DMA Controller (DMAC) 7.3.1 H8S/2456, H8S/2456R, H8S/2454 Group Memory Address Registers (MARA and MARB) MAR is a 32-bit readable/writable register that specifies the source address (transfer source address) or destination address (transfer destination address). MAR consists of two 16-bit registers MARH and MARL. The upper 8 bits of MARH are reserved: they are always read as 0, and cannot be modified.
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H8S/2456, H8S/2456R, H8S/2454 Group 7.3.2 Section 7 DMA Controller (DMAC) I/O Address Registers (IOARA and IOARB) IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the source address (transfer source address) or destination address (transfer destination address). The upper 8 bits of the transfer address are automatically set to H'FF.
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Section 7 DMA Controller (DMAC) 7.3.3 H8S/2456, H8S/2456R, H8S/2454 Group Execute Transfer Count Registers (ETCRA and ETCRB) ETCR is a 16-bit readable/writable register that specifies the number of transfers. The DMA has four ETCR registers: ETCR_0A in channel 0 (channel 0A), ETCR_0B in channel 0 (channel 0B), ETCR_1A in channel 1 (channel 1A), and ETCR_1B in channel 1 (channel 1B). ETCR is not initialized by a reset or in standby mode.
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H8S/2456, H8S/2456R, H8S/2454 Group 7.3.4 Section 7 DMA Controller (DMAC) DMA Control Registers (DMACRA and DMACRB) DMACR controls the operation of each DMAC channel. The DMA has four DMACR registers: DMACR_0A in channel 0 (channel 0A), DMACR_0B in channel 0 (channel 0B), DMACR_1A in channel 1 (channel 1A), and DMACR_1B in channel 1 (channel 1B). In short address mode, channels A and B operate independently, and in full address mode, channels A and B operate together.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 5 RPE 0 R/W Repeat Enable Used in combination with the DTIE bit in DMABCR to select the mode (sequential, idle, or repeat) in which transfer is to be performed.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTF3 0 R/W Data Transfer Factor 3 to 0 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W These bits select the data transfer factor (activation source). There are some differences in activation sources for channel A and channel B.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTF3 0 R/W • 2 DTF2 0 R/W 0000: Setting prohibited 1 DTF1 0 R/W 0 DTF0 0 R/W 0001: Activated by conversion end interrupt of A/D converter unit 0 Channel B 0010: Activated by DREQ pin falling edge input (detected as a low level in the first transfer after transfer is enabled)* 0011: Activated by DREQ pin low-level input* 0100: Activated by SCI channel 0 transmit data emp
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H8S/2456, H8S/2456R, H8S/2454 Group (2) • Section 7 DMA Controller (DMAC) Full Address Mode DMACR_0A and DMACR_1A Bit Bit Name Initial Value R/W Description 15 DTSZ 0 R/W Data Transfer Size Selects the size of data to be transferred at one time.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 10 to 8 ⎯ All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0. [Legend] x: Don't care • DMACR_0B and DMACR_1B Bit Bit Name Initial Value R/W Description 7 ⎯ 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTF3 0 R/W Data Transfer Factor 3 to 0 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W These bits select the data transfer factor (activation source). The factors that can be specified differ between normal mode and block transfer mode.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTF3 0 R/W • 2 DTF2 0 R/W 0000: Setting prohibited 1 DTF1 0 R/W 0 DTF0 0 R/W 0001: Activated by A/D converter unit 0 conversion end interrupt Block Transfer Mode 0010: Activated by DREQ pin falling edge input (detected as a low level in the first transfer after transfer is enabled)* 0011: When USBDRQE bit in PFCR3 is 0: Activated by DREQ pin low-level input When USBDRQE
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) [Legend] ×: Don't care Note: * This setting is prohibited when the USBDRQE bit in PFCR3 is 1. 7.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL) DMABCR controls the operation of each DMAC channel. The bit functions in the DMABCR registers differ according to the transfer mode.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 12 SAE0 0 R/W Single Address Enable 0 Specifies whether channel 0B is to be used for transfer in dual address mode or single address mode. This bit is invalid in full address mode.
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H8S/2456, H8S/2456R, H8S/2454 Group • Section 7 DMA Controller (DMAC) DMABCRL Bit Bit Name Initial Value R/W Description 7 DTE1B 0 R/W Data Transfer Enable 1B 6 DTE1A 0 R/W Data Transfer Enable 1A 5 DTE0B 0 R/W Data Transfer Enable 0B 4 DTE0A 0 R/W Data Transfer Enable 0A If the DTE bit is cleared to 0 when DTIE = 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTIE1B 0 R/W Data Transfer End Interrupt Enable 1B 2 DTIE1A 0 R/W Data Transfer End Interrupt Enable 1A 1 DTIE0B 0 R/W Data Transfer End Interrupt Enable 0B 0 DTIE0A 0 R/W Data Transfer End Interrupt Enable 0A These bits enable or disable an interrupt to the CPU or DTC when transfer ends.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 13, 12 ⎯ All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0. 11 DTA1 0 R/W Data Transfer Acknowledge 1 These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR of channel 1.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 9 DTA0 0 R/W Data Transfer Acknowledge 0 These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR of channel 0. It the DTA0 bit is set to 1 when DTE0 = 1, the internal interrupt source is cleared automatically by DMA transfer.
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H8S/2456, H8S/2456R, H8S/2454 Group • Section 7 DMA Controller (DMAC) DMABCRL Bit Bit Name Initial Value R/W Description 7 DTME1 0 R/W Data Transfer Master Enable 1 Together with the DTE1 bit, this bit controls enabling or disabling of data transfer on channel 1. When both the DTME1 bit and DTE1 bit are set to 1, transfer is enabled for channel 1.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 6 DTE1 0 R/W Data Transfer Enable 1 Enables or disables DMA transfer for the activation source selected by the DTF3 to DTF0 bits in DMACR of channel 1. When DTE1 = 0, data transfer is disabled and the activation source is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 5 DTME0 0 R/W Data Transfer Master Enable 0 Together with the DTE0 bit, this bit controls enabling or disabling of data transfer on channel 0. When both the DTME0 bit and DTE0 bit are set to 1, transfer is enabled for channel 0.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 4 DTE0 0 R/W Data Transfer Enable 0 Enables or disables DMA transfer for the activation source selected by the DTF3 to DTF0 bits in DMACR of channel 0. When DTE0 = 0, data transfer is disabled and the activation source is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 2 DTIE1A 0 R/W Data Transfer End Interrupt Enable 1A Enables or disables an interrupt to the CPU or DTC when transfer ends. If the DTE1 bit is cleared to 1 when DTIE1A = 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) 7.3.6 DMA Write Enable Register (DMAWER) The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and then reactivate the DTC. DMAWER applies restrictions for changing all bits of DMACR, and specific bits for DMATCR and DMABCR for the specific channel, to prevent inadvertent rewriting of registers other than those for the channel concerned.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Figure 7.2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt request, and reactivating channel 0A. The address register and count register areas are set again during the first DTC transfer, then the control register area is set again during the second DTC chain transfer.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) MAR, IOAR, and ETCR can always be written to regardless of the DMAWER settings. When modifying these registers, the channel to be modified should be halted. 7.3.7 DMA Terminal Control Register (DMATCR) DMATCR controls enabling or disabling of output from the DMAC transfer end pin. A port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit.
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H8S/2456, H8S/2456R, H8S/2454 Group 7.4 Section 7 DMA Controller (DMAC) Activation Sources DMAC activation sources consist of internal interrupt requests, external requests, and autorequests. The DMAC activation sources that can be specified depend on the transfer mode and channel, as shown in table 7.3. Table 7.
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Section 7 DMA Controller (DMAC) 7.4.1 H8S/2456, H8S/2456R, H8S/2454 Group Activation by Internal Interrupt Request An interrupt request selected as a DMAC activation source can also simultaneously generate an interrupt request for the CPU or DTC. For details, see section 5, Interrupt Controller. With activation by an internal interrupt request, the DMAC accepts the interrupt request independently of the interrupt controller. Consequently, interrupt controller priority settings are irrelevant.
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H8S/2456, H8S/2456R, H8S/2454 Group 7.4.2 Section 7 DMA Controller (DMAC) Activation by External Request If an external request (DREQ pin) is specified as a DMAC activation source, the relevant port should be set to input mode in advance*. Level sensing or edge sensing can be used for external requests. External request operation in normal mode of short address mode or full address mode is described below.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Table 7.4 DMAC Transfer Modes Transfer Mode Transfer Source Remarks Short address mode • TPU channel 0 to 5 compare match/input capture A interrupt • Up to 4 channels can operate independently Dual address mode • 1-byte or 1-word transfer for a single transfer request • Specify source and destination addresses to transfer data in two bus cycles.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Transfer Mode Transfer Source Remarks Full address mode • Auto-request • Max.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) 7.5.2 Sequential Mode Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.
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H8S/2456, H8S/2456R, H8S/2454 Group Address T Section 7 DMA Controller (DMAC) Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID · (2DTSZ · (N – 1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7.3 Operation in Sequential Mode The number of transfers is specified as 16 bits in ETCR.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Sequential mode setting Set DMABCRH [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR.
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H8S/2456, H8S/2456R, H8S/2454 Group Table 7.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Figure 7.6 shows an example of the setting procedure for idle mode. [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Idle mode setting Set DMABCRH [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR.
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H8S/2456, H8S/2456R, H8S/2454 Group 7.5.4 Section 7 DMA Controller (DMAC) Repeat Mode Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit in DMABCRL to 0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCRL. On completion of the specified number of transfers, MAR and ETCRL are automatically restored to their original settings and operation continues.
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Section 7 DMA Controller (DMAC) H8S/2456, H8S/2456R, H8S/2454 Group In repeat mode, ETCRL functions as the transfer counter, and ETCRH is used to hold the number of transfers. ETCRL is decremented by 1 each time a data transfer is executed, and when its value reaches H'00, it is loaded with the value in ETCRH. At the same time, the value set in MAR is restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR restoration operation is as shown below.
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H8S/2456, H8S/2456R, H8S/2454 Group Address T Section 7 DMA Controller (DMAC) Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID · (2DTSZ · (N – 1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Figure 7.8 shows an example of the setting procedure for repeat mode. [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Repeat mode setting Set DMABCRH [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in both ETCRH and ETCRL.
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H8S/2456, H8S/2456R, H8S/2454 Group 7.5.5 Section 7 DMA Controller (DMAC) Single Address Mode Single address mode can only be specified for channel B. This mode can be specified by setting the SAE bit in DMABCRH to 1 in short address mode. One address is specified by MAR, and the other is set automatically to the data transfer acknowledge pin (DACK). The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.8 summarizes register functions in single address mode. Table 7.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Address T DACK Transfer 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID · (2DTSZ · (N – 1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7.9 Operation in Single Address Mode (When Sequential Mode Is Specified) Figure 7.10 shows an example of the setting procedure for single address mode (when sequential mode is specified).
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Single address mode setting Set DMABCRH Set transfer source and transfer destination addresses [1] [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Set the SAE bit to 1 to select single address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [2] Set the transfer source address/transfer destination address in MAR.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) 7.5.6 Normal Mode In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by setting the FAE bit in DMABCRH to 1 and clearing the BLKE bit in DMACRA to 0. In normal mode, MAR is updated after data transfer of a byte or word in response to a single transfer request, and this is executed the number of times specified in ETCRA.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Transfer Address TA Address BB Address BA Legend: Address Address Address Address Where : TA TB BA BB LA LB N Address TB = LA = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (N – 1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (N – 1)) = Value set in MARA = Value set in MARB = Value set in ETCRA Figure 7.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Figure 7.12 shows an example of the setting procedure for normal mode. [1] Set each bit in DMABCRH. • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Normal mode setting Set DMABCRH [1] [2] Set the transfer source address in MARA, and the transfer destination address in MARB. [3] Set the number of transfers in ETCRA.
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H8S/2456, H8S/2456R, H8S/2454 Group 7.5.7 Section 7 DMA Controller (DMAC) Block Transfer Mode In block transfer mode, data transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCRH and the BLKE bit in DMACRA to 1. In block transfer mode, a data transfer of the specified block size is carried out in response to a single transfer request, and this is executed for the number of times specified in ETCRB.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Figure 7.13 illustrates operation in block transfer mode when MARB is designated as a block area.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Figure 7.14 illustrates operation in block transfer mode when MARA is designated as a block area.
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Section 7 DMA Controller (DMAC) H8S/2456, H8S/2456R, H8S/2454 Group ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00. ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register for which a block designation has been given by the BLKDIR bit in DMACRA is restored in accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Figure 7.15 shows the operation flow in block transfer mode.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmit data empty and receive data full interrupts, EP1FIFO full interrupt and EP2FIFO empty interrupt of the USB, and TPU channel 0 to 5 compare match/input capture A interrupts. Figure 7.16 shows an example of the setting procedure for block transfer mode. [1] Set each bit in DMABCRH.
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H8S/2456, H8S/2456R, H8S/2454 Group 7.5.8 Section 7 DMA Controller (DMAC) Basic Bus Cycles An example of the basic DMAC bus cycle timing is shown in figure 7.17. In this example, wordsize transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed. The bus is not released in response to another bus request, etc., between these read and write operations.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) 7.5.9 (1) DMA Transfer (Dual Address Mode) Bus Cycles Short Address Mode Figure 7.18 shows a transfer example in which TEND output is enabled and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal I/O space.
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H8S/2456, H8S/2456R, H8S/2454 Group (2) Section 7 DMA Controller (DMAC) Full Address Mode (Cycle Steal Mode) Figure 7.19 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) (3) Full Address Mode (Burst Mode) Figure 7.20 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (burst mode) is performed from external 16-bit, 2-state access space to external 16bit, 2-state access space. DMA read DMA write DMA read DMA write DMA read DMA write DMA dead φ Address bus RD HWR LWR TEND Last transfer cycle Bus release Bus release Burst transfer Figure 7.
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H8S/2456, H8S/2456R, H8S/2454 Group (4) Section 7 DMA Controller (DMAC) Full Address Mode (Block Transfer Mode) Figure 7.21 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) DREQ Pin Falling Edge Activation Timing (5) Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected. Figure 7.22 shows an example of normal mode transfer activated by the DREQ pin falling edge.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Figure 7.23 shows an example of block transfer mode transfer activated by the DREQ pin falling edge.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) DREQ Pin Low Level Activation Timing (Normal Mode) (6) Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected. Figure 7.24 shows an example of normal mode transfer activated by the DREQ pin low level.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Figure 7.25 shows an example of block transfer mode transfer activated by DREQ pin low level.
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H8S/2456, H8S/2456R, H8S/2454 Group 7.5.10 (1) Section 7 DMA Controller (DMAC) DMA Transfer (Single Address Mode) Bus Cycles Single Address Mode (Read) Figure 7.26 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) DMA read DMA read DMA read DMA dead φ Address bus RD DACK TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.27 Example of Single Address Mode (Word Read) Transfer A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
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H8S/2456, H8S/2456R, H8S/2454 Group (2) Section 7 DMA Controller (DMAC) Single Address Mode (Write) Figure 7.28 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write DMA write DMA write DMA DMA write dead φ Address bus HWR LWR DACK TEND Bus release Bus release Bus release Bus Last transfer release cycle Bus release Figure 7.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) DMA write DMA write DMA write DMA dead φ Address bus HWR LWR DACK TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.29 Example of Single Address Mode Transfer (Word Write) A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
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H8S/2456, H8S/2456R, H8S/2454 Group (3) Section 7 DMA Controller (DMAC) DREQ Pin Falling Edge Activation Timing Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected. Figure 7.30 shows an example of single address mode transfer activated by the DREQ pin falling edge.
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Section 7 DMA Controller (DMAC) H8S/2456, H8S/2456R, H8S/2454 Group DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) DREQ Pin Low Level Activation Timing (4) Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected. Figure 7.31 shows an example of single address mode transfer activated by the DREQ pin low level.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the single cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. 7.5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) Figure 7.33 shows an example of single address transfer using the write data buffer function. In this example, the CPU program area is in on-chip memory. DMA read DMA single CPU read DMA single CPU read φ Internal address Internal read signal External address RD DACK Figure 7.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) If transfer requests are issued simultaneously for more than one channel, or if a transfer request for another channel is issued during a transfer, when the bus is released, the DMAC selects the highest-priority channel from among those issuing a request according to the priority order shown in table 7.11.
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H8S/2456, H8S/2456R, H8S/2454 Group 7.5.13 Section 7 DMA Controller (DMAC) Relation between DMAC and External Bus Requests, Refresh Cycles, and EXDMAC* When the DMAC accesses external space, contention with a refresh cycle, EXDMAC cycle*, or external bus release cycle may arise.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) 7.5.14 DMAC and NMI Interrupts When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An NMI interrupt does not affect the operation of the DMAC in other modes. In full address mode, transfer is enabled for a channel when both the DTE bit and DTME bit in DMABCRL are set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested.
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H8S/2456, H8S/2456R, H8S/2454 Group 7.5.15 Section 7 DMA Controller (DMAC) Forced Termination of DMAC Operation If the DTE bit in DMABCRL is cleared to 0 for the channel currently operating, the DMAC stops on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the DTE bit is set to 1 again. In full address mode, the same applies to the DTME bit in DMABCRL. Figure 7.36 shows the procedure for forcibly terminating DMAC operation by software.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) 7.5.16 Clearing Full Address Mode Figure 7.37 shows the procedure for releasing and initializing a channel designated for full address mode. After full address mode has been cleared, the channel can be set to another transfer mode using the appropriate setting procedure. [1] Clear both the DTE bit and DTME bit in DMABCRL to 0, or wait until the transfer ends and the DTE bit is cleared to 0, then clear the DTME bit to 0.
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H8S/2456, H8S/2456R, H8S/2454 Group 7.6 Section 7 DMA Controller (DMAC) Interrupt Sources The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.12 shows the interrupt sources and their priority order. Table 7.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) 7.7 (1) Usage Notes DMAC Register Access during Operation Except for forced termination of the DMAC, the operating (including transfer waiting state) channel setting should not be changed. The operating channel setting should only be changed when transfer is disabled. Also, DMAC registers should not be written to in a DMA transfer. DMAC register reads during operation (including the transfer waiting state) are described below.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) • If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC register is read as shown in figure 7.40. DMA transfer cycle CPU longword read MAR upper word read MAR lower word read DMA read DMA write φ DMA internal address DMA control DMA register operation Idle [1] Transfe source Transfer destination Read Write Idle [2] Note: The lower word of MAR is the updated value after the operation in [1].
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Section 7 DMA Controller (DMAC) (3) H8S/2456, H8S/2456R, H8S/2454 Group Write Data Buffer Function When the WDBE bit of BCR in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 7 DMA Controller (DMAC) However, if the last transfer cycle and a CBR refresh occur simultaneously, note that although the CBR refresh and the last transfer cycle may be executed consecutively, TEND may also go low in this case for the refresh cycle. Note: * Not supported by the H8S/2454 Group. DMA read DMA write φ Internal address Internal read signal Internal write signal External address HWR, LWR TEND Not output External write by CPU, etc. Figure 7.
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Section 7 DMA Controller (DMAC) (6) H8S/2456, H8S/2456R, H8S/2454 Group Activation Source Acceptance At the start of activation source acceptance, a low level is detected in both DREQ pin falling edge sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request is detected. Therefore, a request is accepted from an internal interrupt or DREQ pin low level that occurs before write to DMABCRL to enable transfer.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) Section 8 EXDMA Controller (EXDMAC) This LSI has a built-in dual-channel external bus transfer DMA controller (EXDMAC). The EXDMAC can carry out high-speed data transfer, in place of the CPU, to and from external devices and external memory with a DACK (EXDMA transfer notification) facility. Note: This EXDMAC is not supported by the H8S/2454 Group. 8.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) Figure 8.1 shows a block diagram of the EXDMAC.
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H8S/2456, H8S/2456R, H8S/2454 Group 8.2 Section 8 EXDMA Controller (EXDMAC) Input/Output Pins Table 8.1 shows the pin configuration of the EXDMAC. Table 8.
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Section 8 EXDMA Controller (EXDMAC) 8.3 H8S/2456, H8S/2456R, H8S/2454 Group Register Descriptions The EXDMAC has the following registers.
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H8S/2456, H8S/2456R, H8S/2454 Group 8.3.1 Section 8 EXDMA Controller (EXDMAC) EXDMA Source Address Register (EDSAR) EDSAR is a 32-bit readable/writable register that specifies the transfer source address. An address update function is provided that updates the register contents to the next transfer source address each time transfer processing is performed. In single address mode, the EDSAR value is ignored when a device with DACK is specified as the transfer source.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) 8.3.3 EXDMA Transfer Count Register (EDTCR) EDTCR specifies the number of transfers. The function differs according to the transfer mode. Do not write to EDTCR for a channel on which EXDMA transfer is in progress. (1) Normal Transfer Mode Bit Bit Name Initial Value R/W Description 31 to 24 ⎯ All 0 ⎯ Reserved These bits are always read as 0 and cannot be modified.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) (2) Block Transfer Mode Bit Bit Name Initial Value R/W Description 31 to 24 ⎯ All 0 ⎯ Reserved These bits are always read as 0 and cannot be modified. 23 to 16 Undefined R/W Block Size These bits specify the block size (number of bytes or number of words) for block transfer. Setting H'01 specifies one as the block, while setting H'00 specifies the maximum block size, that is 256.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) 8.3.4 EXDMA Mode Control Register (EDMDR) EDMDR controls EXDMAC operations. Bit Bit Name Initial Value R/W Description 15 EDA 0 R/(W) EXDMA Active Enables or disables data transfer on the corresponding channel. When this bit is set to 1, this indicates that an EXDMA operation is in progress. When auto request mode is specified (by bits MDS1 and MDS0), transfer processing begins when this bit is set to 1.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 14 BEF 0 R/(W)* Block Transfer Error Flag Flag that indicates the occurrence of an error during block transfer. If an NMI interrupt is generated during block transfer, the EXDMAC immediately terminates the EXDMA operation and sets this bit to 1.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 10 AMS 0 R/W Address Mode Select Selects single address mode or dual address mode. When single address mode is selected, the EDACK pin is valid. 0: Dual address mode 1: Single address mode 9 MDS1 0 R/W Mode Select 1 and 0 8 MDS0 0 R/W These bits specify the activation source, bus mode, and transfer mode.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 6 IRF 0 R/(W)* Interrupt Request Flag Flag indicating that an interrupt request has occurred and transfer has ended.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 3 DTSIZE 0 R/W Data Transmit Size Specifies the size of data to be transferred. 0: Byte-size 1: Word-size 2 BGUP 0 R/W Bus Give-Up When this bit is set to 1, the bus can be transferred to an internal bus master in burst mode or block transfer mode. This setting is ignored in normal mode and cycle steal mode.
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H8S/2456, H8S/2456R, H8S/2454 Group 8.3.5 Section 8 EXDMA Controller (EXDMAC) EXDMA Address Control Register (EDACR) EDACR specifies address register incrementing/decrementing and use of the repeat area function. Bit Bit Name Initial Value R/W Description 15 SAT1 0 R/W Source Address Update Mode 14 SAT0 0 R/W These bits specify incrementing/decrementing of the transfer source address (EDSAR).
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 12 SARA4 0 R/W Source Address Repeat Area 11 SARA3 0 R/W 10 SARA2 0 R/W 9 SARA1 0 R/W 8 SARA0 0 R/W These bits specify the source address (EDSAR) repeat area. The repeat area function updates the specified lower address bits, leaving the remaining upper address bits always the same. A repeat area size of 2 bytes to 8 Mbytes can be specified.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 7 DAT1 0 R/W Destination Address Update Mode 6 DAT0 0 R/W These bits specify incrementing/decrementing of the transfer destination address (EDDAR). When an external device with DACK is designated as the transfer destination in single address mode, the specification by these bits is ignored.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 4 DARA4 0 R/W Destination Address Repeat Area 3 DARA3 0 R/W 2 DARA2 0 R/W 1 DARA1 0 R/W 0 DARA0 0 R/W These bits specify the destination address (EDDAR) repeat area. The repeat area function updates the specified lower address bits, leaving the remaining upper address bits always the same. A repeat area size of 2 bytes to 8 Mbytes can be specified.
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H8S/2456, H8S/2456R, H8S/2454 Group 8.4 Operation 8.4.1 Transfer Modes Section 8 EXDMA Controller (EXDMAC) The transfer modes of the EXDMAC are summarized in table 8.2. Table 8.
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Section 8 EXDMA Controller (EXDMAC) H8S/2456, H8S/2456R, H8S/2454 Group In block transfer mode, a transfer of the specified block size is executed in response to one transfer request. The block size can be from 1 to 256 bytes or words. Within a block, transfer can be performed at the same high speed as in block transfer mode.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) Figure 8.2 shows an example of the timing in dual address mode. EXDMA read cycle EXDMA write cycle φ Address bus EDSAR EDDAR RD WR ETEND Figure 8.2 Example of Timing in Dual Address Mode (2) Single Address Mode In single address mode, the EDACK signal is used instead of the source or destination address register to transfer data directly between an external device and external memory.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) Figure 8.3 shows the data flow in single address mode, and figure 8.4 shows an example of the timing. External address bus External data bus Microcomputer External memory EXDMAC External device with DACK EDACK EDREQ Data flow Figure 8.3 Data Flow in Single Address Mode Page 426 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) Transfer from external memory to external device with DACK EXDMA cycle φ Address bus EDSAR RD Address to external memory space RD signal to external memory space WR EDACK Data output from external memory Data bus ETEND Transfer from external device with DACK to external memory EXDMA cycle φ Address bus EDDAR Address to external memory space RD WR WR signal to external memory space EDACK Data output from external device with
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Section 8 EXDMA Controller (EXDMAC) 8.4.3 (1) H8S/2456, H8S/2456R, H8S/2454 Group EXDMA Transfer Requests Auto Request Mode In auto request mode, transfer request signals are automatically generated within the EXDMAC in cases where a transfer request signal is not issued from outside, such as in transfer between two memories, or between a peripheral module that is not capable of generating transfer requests and memory. In auto request mode, transfer is started when the EDA bit is set to 1 in EDMDR.
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H8S/2456, H8S/2456R, H8S/2454 Group 8.4.4 Section 8 EXDMA Controller (EXDMAC) Bus Modes There are two bus modes: cycle steal mode and burst mode. When the activation source is an auto request, either cycle steal mode or burst mode can be selected. When the activation source is an external request, cycle steal mode is used. (1) Cycle Steal Mode In cycle steal mode, the EXDMAC releases the bus at the end of each transfer of a transfer unit (byte, word, or block).
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) (2) Burst Mode In burst mode, once the EXDMAC acquires the bus it continues transferring data, without releasing the bus, until the transfer end condition is satisfied. There is no burst mode in external request mode. In burst mode, once transfer is started it is not interrupted even if there is a transfer request from another channel with higher priority.
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H8S/2456, H8S/2456R, H8S/2454 Group 8.4.5 Section 8 EXDMA Controller (EXDMAC) Transfer Modes There are two transfer modes: normal transfer mode and block transfer mode. When the activation source is an external request, either normal transfer mode or block transfer mode can be selected. When the activation source is an auto request, normal transfer mode is used. (1) Normal Transfer Mode In normal transfer mode, transfer of one transfer unit is processed in response to one transfer request.
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Section 8 EXDMA Controller (EXDMAC) (2) H8S/2456, H8S/2456R, H8S/2454 Group Block Transfer Mode In block transfer mode, the number of bytes or words specified by the block size is transferred in response to one transfer request. The upper 8 bits of EDTCR specify the block size, and the lower 16 bits function as a 16-bit transfer counter. A block size of 1 to 256 can be specified. During transfer of a block, transfer requests for other higher-priority channels are held pending.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) EDREQ EDRAK One-block transfer cycle Bus cycle CPU CPU CPU EXDMAC EXDMAC EXDMAC CPU CPU cycle not generated ETEND Transfer conditions: · Single address mode · BGUP = 0 · Block size (EDTCR[23:16]) = 3 Figure 8.8 Example of Timing in Block Transfer Mode R01UH0309EJ0500 Rev. 5.
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Section 8 EXDMA Controller (EXDMAC) 8.4.6 H8S/2456, H8S/2456R, H8S/2454 Group Repeat Area Function The EXDMAC has a function for designating a repeat area for source addresses and/or destination addresses. When a repeat area is designated, the address register values repeat within the range specified as the repeat area.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) When lower 3 bits (8-byte area) of EDSAR are designated as repeat area (SARA4 to SARA0 = 3) External memory : Range of EDSAR values H'23FFFE H'23FFFF H'240000 H'240000 H'240001 H'240001 H'240002 H'240002 H'240003 H'240003 H'240004 H'240004 H'240005 H'240005 H'240006 H'240006 H'240007 H'240007 H'240008 H'240009 Repeated Repeat area overflow interrupt can be requested : Figure 8.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) When lower 3 bits (8-byte area) of EDSAR are designated as repeat area (SARA4 to SARA0 = 3), and block size of 5 (EDTCR[23–16] = 5) is set in block transfer mode External memory Range of EDSAR values First block transfer Second block transfer H'240000 H'240000 H'240000 H'240000 H'240001 H'240001 H'240001 H'240001 H'240002 H'240002 H'240002 H'240003 H'240003 H'240003 H'240004 H'240004 H'240004 H'240005 H'240005 H
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H8S/2456, H8S/2456R, H8S/2454 Group 8.4.7 Section 8 EXDMA Controller (EXDMAC) Registers during EXDMA Transfer Operation EXDMAC register values are updated as EXDMA transfer processing is performed. The updated values depend on various settings and the transfer status.
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Section 8 EXDMA Controller (EXDMAC) H8S/2456, H8S/2456R, H8S/2454 Group When EDDAR is read during a transfer operation, a longword access must be used. During a transfer operation, EDDAR may be updated without regard to accesses from the CPU, and the correct values may not be read if the upper and lower words are read separately. In a longword access, the EXDMAC buffers the EDDAR value to ensure that the correct value is output.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) Figure 8.11 shows EDTCR update operations in normal transfer mode and block transfer mode.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) When transfer is halted by writing 0 to the EDA bit, the EDA bit remains at 1 during the EXDMA transfer period. In block transfer mode, since a block-size transfer is carried out without interruption, the EDA bit remains at 1 from the time 0 is written to it until the end of the current block-size transfer. In burst mode, transfer is halted for up to three EXDMA transfers following the bus cycle in which 0 is written to the EDA bit.
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H8S/2456, H8S/2456R, H8S/2454 Group (5) Section 8 EXDMA Controller (EXDMAC) BEF Bit in EDMDR In block transfer mode, the specified number of transfers (equivalent to the block size) is performed in response to a single transfer request. To ensure that the correct number of transfers is carried out, a block-size transfer is always executed, except in the event of a reset, transition to standby mode, or generation of an NMI interrupt.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) (1) Transfer Requests from Multiple Channels (Except Auto Request Cycle Steal Mode) If transfer requests for different channels are issued during a transfer operation, the highestpriority channel (excluding the currently transferring channel) is selected. The selected channel begins transfer after the currently transferring channel releases the bus.
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H8S/2456, H8S/2456R, H8S/2454 Group (2) Section 8 EXDMA Controller (EXDMAC) Transfer Requests from Multiple Channels in Auto Request Cycle Steal Mode If transfer requests for different channels are issued during a transfer in auto request cycle steal mode, the operation depends on the channel priority. If the channel that made the transfer request is of higher priority than the channel currently performing transfer, the channel that made the transfer request is selected.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) Figure 8.14 shows examples of transfer timing in cases that include auto request cycle steal mode.
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H8S/2456, H8S/2456R, H8S/2454 Group 8.4.9 (1) Section 8 EXDMA Controller (EXDMAC) EXDMAC Bus Cycles (Dual Address Mode) Normal Transfer Mode (Cycle Steal Mode) Figure 8.15 shows an example of transfer when ETEND output is enabled, and word-size, normal transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. After one byte or word has been transferred, the bus is released.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) (2) Normal Transfer Mode (Burst Mode) Figure 8.16 shows an example of transfer when ETEND output is enabled, and word-size, normal transfer mode (burst mode) is performed from external 16-bit, 2-state access space to external 16bit, 2-state access space. In burst mode, one-byte or one-word transfers are executed continuously until transfer ends.
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H8S/2456, H8S/2456R, H8S/2454 Group (3) Section 8 EXDMA Controller (EXDMAC) Block Transfer Mode (Cycle Steal Mode) Figure 8.17 shows an example of transfer when ETEND output is enabled, and word-size, block transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. One block is transferred in response to one transfer request, and after the transfer, the bus is released.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) (4) EDREQ Pin Falling Edge Activation Timing Figure 8.18 shows an example of normal mode transfer activated by the EDREQ pin falling edge.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) One block transfer One block transfer EXDMA read EXDMA write Transfer source Transfer destination Bus release EXDMA read Bus release EXDMA write Bus release φ EDREQ Address bus EXDMA control Idle Read Channel Idle Minimum 3 cycles [2] [3] Idle Request clearance period Request Minimum 3 cycles [4] Acceptance resumed [1] [2], [5] [3], [6] [4], [7] Transfer destination Read Write Request clearance period Request [
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) (5) EDREQ Pin Low Level Activation Timing Figure 8.20 shows an example of normal mode transfer activated by the EDREQ pin low level.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) One block transfer EXDMA read Bus release One block transfer EXDMA write EXDMA read Bus release EXDMA write Bus release φ EDREQ Address bus Transfer source EXDMA control Idle Read Channel Write Transfer destination Transfer source Read Write Idle Request clearance period Request [2] [3] Minimum 3 cycles [4] Acceptance resumed [1] [2], [5] [3], [6] [4], [7] Idle Request clearance period Request Minimum 3 cycle
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) 8.4.10 (1) EXDMAC Bus Cycles (Single Address Mode) Single Address Mode (Read) Figure 8.22 shows an example of transfer when ETEND output is enabled, and byte-size, single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) After one byte or word has been transferred in response to one transfer request, the bus is released. While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated. (2) Single Address Mode (Write) Figure 8.24 shows an example of transfer when ETEND output is enabled, and byte-size, single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) EXDMA write EXDMA write EXDMA write φ Address bus HWR LWR EDACK ETEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 8.25 Example of Single Address Mode (Word Write) Transfer After one byte or word has been transferred in response to one transfer request, the bus is released. While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated. Page 454 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group (3) Section 8 EXDMA Controller (EXDMAC) EDREQ Pin Falling Edge Activation Timing Figure 8.26 shows an example of single address mode transfer activated by the EDREQ pin falling edge.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) (4) EDREQ Pin Low Level Activation Timing Figure 8.27 shows an example of single address mode transfer activated by the EDREQ pin low level.
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H8S/2456, H8S/2456R, H8S/2454 Group 8.4.11 (1) Section 8 EXDMA Controller (EXDMAC) Examples of Operation Timing in Each Mode Auto Request/Cycle Steal Mode/Normal Transfer Mode When the EDA bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three cycles later. There is a one-cycle bus release interval between the end of a one-transfer-unit EXDMA cycle and the start of the next transfer.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) φ pin 1 bus cycle Bus cycle CPU cycle CPU operation External space EXDMA single transfer cycle CPU cycle External space Last transfer cycle EXDMA single transfer cycle CPU cycle EXDMA single transfer cycle External space CPU cycle External space EDACK ETEND Figure 8.
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H8S/2456, H8S/2456R, H8S/2454 Group (2) Section 8 EXDMA Controller (EXDMAC) Auto Request/Burst Mode/Normal Transfer Mode When the EDA bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three cycles later. Once transfer is started, it continues (as a burst) until the transfer end condition is satisfied. If the BGUP bit is 1 in EDMDR, the bus is transferred in the event of a bus request from another bus master.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) φ pin 1 bus cycle Bus cycle CPU operation CPU cycle CPU cycle External space External space EXDMA read EXDMA write CPU cycle External space 1 bus cycle EXDMA read EXDMA write CPU cycle EXDMA read EXDMA write External space Figure 8.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) φ pin Last transfer cycle Bus cycle Bus release EXDMA single transfer cycle EXDMA single transfer cycle 1 cycle EXDMA single transfer cycle Other channel EXDMA cycle Bus release Bus release Original channel EDACK Original channel ETEND Other channel transfer request (EDREQ) Figure 8.34 Auto Request/Burst Mode/Normal Transfer Mode (Contention with Another Channel/Single Address Mode) R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) (3) External Request/Cycle Steal Mode/Normal Transfer Mode In external request mode, an EXDMA transfer cycle is started a minimum of three cycles after a transfer request is accepted. The next transfer request is accepted after the end of a one-transferunit EXDMA cycle. For external bus space CPU cycles, at least two bus cycles are generated before the next EXDMA cycle.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) φ pin EDREQ EDRAK 2 bus cycles Bus cycle CPU cycle CPU cycle CPU cycle External space CPU operation External space External space EXDMA single transfer cycle Last transfer cycle CPU cycle CPU cycle External space External space EXDMA single transfer cycle CPU cycle External space EDACK ETEND Figure 8.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) φ pin Original channel EDREQ Original channel EDRAK 1 cycle 3 cycles Bus cycle EXDMA transfer cycle Bus release EXDMA read 1 cycle Other channel transfer cycle EXDMA write Bus release EXDMA read EXDMA write Bus release Other channel EDREQ Other channel EDRAK Figure 8.
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R01UH0309EJ0500 Rev. 5.00 Sep 24, 2012 EDA bit ETEND Bus cycle EDRAK EDREQ φ pin 1 Bus release EXDMA read EXDMA write EXDMA read EXDMA write EXDMA read EXDMA write Last transfer in block Repeated 1-block-size transfer period Bus release 3 cycles EXDMA read EXDMA write Repeated EXDMA read 0 EXDMA write Bus release Last transfer cycle Last block H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) Figure 8.
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Page 466 of 1408 ETEND EDACK Bus cycle EDRAK EDREQ φ pin Bus release EXDMA single transfer cycle EXDMA single transfer cycle EXDMA single transfer cycle Last transfer in block Repeated 1-block-size transfer period Bus release 3 cycles EXDMA single transfer cycle Repeated EXDMA single transfer cycle Bus release Last transfer cycle Last block Section 8 EXDMA Controller (EXDMAC) H8S/2456, H8S/2456R, H8S/2454 Group Figure 8.
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R01UH0309EJ0500 Rev. 5.
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Page 468 of 1408 External space CPU operation ETEND CPU cycle Bus cycle EDRAK EDREQ φ pin External space CPU cycle External space CPU cycle External space EXDMA read EXDMA write CPU cycle 1 bus cycle External space EXDMA read EXDMA write CPU cycle 1 bus cycle External space CPU cycle 1 bus cycle Repeated EXDMA read 1-block-size transfer period External space EXDMA read EXDMA write Last transfer in block CPU cycle External space CPU cycle Section 8 EXDMA Controller (EXDMAC)
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R01UH0309EJ0500 Rev. 5.
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Page 470 of 1408 Other channel EDRAK Other channel EDREQ ETEND Bus cycle EDRAK EDREQ φ pin Bus release EXDMA read EXDMA write Repeated EXDMA read EXDMA write Last transfer in block 1-block-size transfer period Bus release Other channel EXDMA cycle Bus release EXDMA read EXDMA write Repeated EXDMA read EXDMA write Last transfer in block 1-block-size transfer period Section 8 EXDMA Controller (EXDMAC) H8S/2456, H8S/2456R, H8S/2454 Group Figure 8.
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H8S/2456, H8S/2456R, H8S/2454 Group 8.4.12 Section 8 EXDMA Controller (EXDMAC) Ending EXDMA Transfer The operation for ending EXDMA transfer depends on the transfer end conditions. When EXDMA transfer ends, the EDA bit in EDMDR changes from 1 to 0, indicating that EXDMA transfer has ended. (1) Transfer End by 1 → 0 Transition of EDTCR When the value of EDTCR changes from 1 to 0, EXDMA transfer ends on the corresponding channel and the EDA bit in EDMDR is cleared to 0.
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Section 8 EXDMA Controller (EXDMAC) (4) H8S/2456, H8S/2456R, H8S/2454 Group Transfer Abort by NMI Interrupt EXDMA transfer is aborted when an NMI interrupt is generated. The EDA bit is cleared to 0 in all channels. In external request mode, EXDMA transfer is performed for all transfer requests for which EDRAK has been output. In dual address mode, processing is executed for the write cycle following the read cycle. In block transfer mode, operation is aborted even in the middle of a block-size transfer.
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H8S/2456, H8S/2456R, H8S/2454 Group 8.5 Section 8 EXDMA Controller (EXDMAC) Interrupt Sources EXDMAC interrupt sources are a transfer end indicated by the transfer counter, and repeat area overflow interrupts. Table 8.4 shows the interrupt sources and their priority order. Table 8.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 8 EXDMA Controller (EXDMAC) The transfer end interrupt can be cleared either by clearing the IRF bit to 0 in EDMDR within the interrupt handling routine, or by re-setting the transfer counter and address registers and then setting the EDA bit to 1 in EDMDR to perform transfer continuation processing. An example of the procedure for clearing the transfer end interrupt and restarting transfer is shown in figure 8.46.
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H8S/2456, H8S/2456R, H8S/2454 Group 8.6 (1) Section 8 EXDMA Controller (EXDMAC) Usage Notes EXDMAC Register Access during Operation Except for clearing the EDA bit to 0 in EDMDR, settings should not be changed for a channel in operation (including the transfer standby state). Transfer must be disabled before changing a setting for an operational channel. (2) Module Stop State When the MSTP14 bit is set to 1 in MSTPCRH, the EXDMAC clock stops and the EXDMAC enters the module stop state.
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Section 8 EXDMA Controller (EXDMAC) (4) H8S/2456, H8S/2456R, H8S/2454 Group Activation Source Acceptance At the start of activation source acceptance, low level sensing is used for both falling edge sensing and low level sensing on the EDREQ pin. Therefore, a request is accepted in the case of a low level at the EDREQ pin that occurs before execution of the EDMDR write for setting the transferenabled state.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 9 Data Transfer Controller (DTC) Section 9 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 9.1 shows a block diagram of the DTC. 9.1 Features • Transfer possible over any number of channels • Three transfer modes 1. Normal mode One operation transfers one byte or one word of data. Memory address is incremented or decremented by 1 or 2.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 9 Data Transfer Controller (DTC) The DTC's register information is stored in the on-chip RAM. When the DTC is used, the RAME bit in SYSCR and MSTP32 bit in RMMSTPCR must be set to 1 and 0, respectively. A 32-bit bus connects the DTC to the on-chip RAM (1 Kbyte), enabling 32-bit/1-state reading and writing of the DTC register information.
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H8S/2456, H8S/2456R, H8S/2454 Group 9.2 Section 9 Data Transfer Controller (DTC) Register Descriptions DTC has the following registers. • • • • • • DTC mode register A (MRA) DTC mode register B (MRB) DTC source address register (SAR) DTC destination address register (DAR) DTC transfer count register A (CRA) DTC transfer count register B (CRB) These six registers cannot be directly accessed from the CPU.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 9 Data Transfer Controller (DTC) Bit Bit Name Initial Value R/W Description 5 DM1 Undefined ⎯ Destination Address Mode 1 and 0 4 DM0 Undefined ⎯ These bits specify a DAR operation after a data transfer.
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H8S/2456, H8S/2456R, H8S/2454 Group 9.2.2 Section 9 Data Transfer Controller (DTC) DTC Mode Register B (MRB) MRB selects the DTC operating mode. Bit Bit Name Initial Value R/W Description 7 CHNE Undefined ⎯ DTC Chain Transfer Enable When this bit is set to 1, a chain transfer will be performed. For details, refer to section 9.5.4, Chain Transfer.
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Section 9 Data Transfer Controller (DTC) 9.2.3 H8S/2456, H8S/2456R, H8S/2454 Group DTC Source Address Register (SAR) SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 9.2.4 DTC Destination Address Register (DAR) DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. 9.2.
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H8S/2456, H8S/2456R, H8S/2454 Group 9.2.7 Section 9 Data Transfer Controller (DTC) DTC Enable Registers A to I (DTCERA to DTCERI) DTCER which is comprised of registers, DTCERA to DTCERI, is a register that specifies DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is shown in table 9.2. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and writing.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 9 Data Transfer Controller (DTC) 9.2.9 DTC Control Register (DTCCR) DTCCR enables or disables DTC activation by software. Bit Bit Name Initial Value R/W Description 7 SWDTE 0 R/W DTC Software Activation Enable Setting this bit to 1 activates the DTC. Only 1 can be written to this bit.
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H8S/2456, H8S/2456R, H8S/2454 Group 9.3 Section 9 Data Transfer Controller (DTC) Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR or DTCCR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding DTCER bit is cleared.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 9 Data Transfer Controller (DTC) Source flag cleared Clear controller Clear DTCER On-chip peripheral modules IRQ interrupt DTVECR DTCCR Interrupt request Selection circuit Select Clear request DTC CPU Interrupt controller Interrupt mask Figure 9.2 Block Diagram of DTC Activation Source Control Page 486 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group 9.4 Section 9 Data Transfer Controller (DTC) Location of Register Information and DTC Vector Table Locate the register information in the on-chip RAM (addresses: H'FFBC00 to H'FFBFFF). Register information should be located at the address that is multiple of four within the range. Locating the register information in address space is shown in figure 9.3.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 9 Data Transfer Controller (DTC) DTC vector address Register information start address Register information Chain transfer Figure 9.4 Correspondence between DTC Vector Address and Register Information Table 9.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 9 Data Transfer Controller (DTC) Origin of Activation Source Activation Source Vector Number DTC Vector Address DTCE* TPU_0 TGI0A 40 H'0450 DTCEC5 TGI0B 41 H'0452 DTCEC4 TGI0C 42 H'0454 DTCEC3 TGI0D 43 H'0456 DTCEC2 TGI1A 48 H'0460 DTCEC1 TGI1B 49 H'0462 DTCEC0 TGI2A 52 H'0468 DTCED7 TGI2B 53 H'046A DTCED6 TGI3A 56 H'0470 DTCED5 TGI3B 57 H'0472 DTCED4 TGI3C 58 H'0474 DTCED3 TGI3D 59 H'0476 DTCED2 TGI4A 64 H
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H8S/2456, H8S/2456R, H8S/2454 Group Section 9 Data Transfer Controller (DTC) Origin of Activation Source Activation Source Vector Number DTC Vector Address DTCE* SCI_3 RXI3 101 H'04CA DTCEF5 TXI3 102 H'04CC DTCEF4 SCI_4 1 RXI4 105 H'04D2 DTCEG3 TXI4 106 H'04D4 DTCEG2 A/D_1 ADI1 112 H'04E0 DTCEG1 TPU_6 TGI6A 120 H'04F0 DTCEG0 TGI6B 121 H'04F2 DTCEH7 TGI6C 122 H'04F4 DTCEH6 TGI6D 123 H'04F6 DTCEH5 TPU_7 TGI7A 125 H'04FA DTCEH4 TGI7B 126 H'04FC DTCEH3 TP
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H8S/2456, H8S/2456R, H8S/2454 Group 9.5 Section 9 Data Transfer Controller (DTC) Operation The DTC stores register information in the on-chip RAM. When activated, the DTC reads register information that is already stored in the on-chip RAM and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to the onchip RAM.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 9 Data Transfer Controller (DTC) Start Read DTC vector Next transfer Read register information Data transfer Write register information CHNE = 1? Yes No CHNS = 0? Yes Transfer counter = 0 or DISEL = 1? No No Yes Transfer counter = 0? Yes No DISEL = 1? Yes No Clear activation flag Clear DTCER End Interrupt exception handling Figure 9.5 Flowchart of DTC Operation Page 492 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Table 9.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 9 Data Transfer Controller (DTC) 9.5.1 Normal Mode In normal mode, one operation transfers one byte or one word of data. Table 9.4 lists the register function in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number of transfers has ended, a CPU interrupt can be requested. Table 9.
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H8S/2456, H8S/2456R, H8S/2454 Group 9.5.2 Section 9 Data Transfer Controller (DTC) Repeat Mode In repeat mode, one operation transfers one byte or one word of data. Table 9.5 lists the register function in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of transfers has ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 9 Data Transfer Controller (DTC) 9.5.3 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 9.6 lists the register function in block transfer mode. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored.
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H8S/2456, H8S/2456R, H8S/2454 Group 9.5.4 Section 9 Data Transfer Controller (DTC) Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 9.9 shows the operation of chain transfer.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 9 Data Transfer Controller (DTC) 9.5.5 Interrupt Sources An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 9 Data Transfer Controller (DTC) φ DTC activation request DTC request Data transfer Vector read Read Write Read Write Address Transfer information read Transfer information write Figure 9.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 9 Data Transfer Controller (DTC) Table 9.7 DTC Execution Status Mode Vector Read I Register Information Read/Write Data Read J K Data Write L Internal Operations M Normal 1 6 1 1 3 Repeat 1 6 1 1 3 Block transfer 1 6 N N 3 [Legend] N: Block size (initial setting of CRAH and CRAL) Table 9.
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H8S/2456, H8S/2456R, H8S/2454 Group 9.6 Procedures for Using DTC 9.6.1 Activation by Interrupt Section 9 Data Transfer Controller (DTC) The procedure for using the DTC with interrupt activation is as follows: 1. 2. 3. 4. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. Set the start address of the register information in the DTC vector address. Set the corresponding bit in DTCER to 1.
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Section 9 Data Transfer Controller (DTC) 9.7 Examples of Use of the DTC 9.7.1 Normal Mode H8S/2456, H8S/2456R, H8S/2454 Group An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0).
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H8S/2456, H8S/2456R, H8S/2454 Group 9.7.2 Section 9 Data Transfer Controller (DTC) Chain Transfer An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle updating. Repeat mode transfer to NDR of the PPG is performed in the first half of the chain transfer, and normal mode transfer to the TPU's TGR in the second half.
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Section 9 Data Transfer Controller (DTC) 9.7.3 H8S/2456, H8S/2456R, H8S/2454 Group Chain Transfer when Counter = 0 By executing a second data transfer, and performing re-setting of the first data transfer, only when the counter value is 0, it is possible to perform 256 or more repeat transfers. An example is shown in which a 128-Kbyte input buffer is configured. The input buffer is assumed to have been set to start at lower address H'0000. Figure 9.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 9 Data Transfer Controller (DTC) Input circuit Input buffer First data transfer register information Chain transfer (counter = 0) Second data transfer register information Upper 8 bits of DAR Figure 9.13 Chain Transfer when Counter = 0 R01UH0309EJ0500 Rev. 5.
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Section 9 Data Transfer Controller (DTC) 9.7.4 H8S/2456, H8S/2456R, H8S/2454 Group Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. 1.
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H8S/2456, H8S/2456R, H8S/2454 Group 9.8 Usage Notes 9.8.1 Module Stop Function Setting Section 9 Data Transfer Controller (DTC) DTC operation can be disabled or enabled using the module stop control register. The initial setting is for DTC operation to be enabled. Register access is disabled by setting the module stop state. The module stop state cannot be set while the DTC is activated. For details, refer to section 24, Power-Down Modes. 9.8.
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Section 9 Data Transfer Controller (DTC) Page 508 of 1408 H8S/2456, H8S/2456R, H8S/2454 Group R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports Section 10 I/O Ports Table 10.1 summarizes the port functions of the H8S/2456 Group and H8S/2456R Group. Table 10.2 summarizes the port functions of the H8S/2454 Group. The pins of each port also have other functions such as input/output or external interrupt input pins of on-chip peripheral modules.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports Table 10.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports Mode 3, 7 Port Description Mode 1 Port 4 General I/O port also P47/AN7_0 functioning as A/D converter analog inputs P46/AN6_0 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Schmitt- Input Open triggered input Pin*2 Pull-up MOS Capability Drain Output Capability 5-V ⎯ ⎯ ⎯ ⎯ IRQ3-A ⎯ All output pin functions ⎯ Tolerance P45/AN5_0 P44/AN4_0 P43/AN3_0 P42/AN2_0 P41/AN1_0 P40/AN0_0 Port 5 General I/O port also functioning as interrupt inpu
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports Mode 3, 7 Mode 2 Mode 4 Schmitt- Input Open triggered input Pin*2 Pull-up MOS Capability Drain Output Capability 5-V ⎯ All output ⎯ Port Description Mode 1 Port 8 General I/O port also P85/IRQ5-B/PO5-B/TIOCB4-B/TMO1-B/SCK3/ P85/IRQ5-B/ IRQ5-B, functioning as EXDMAC I/Os, PPG outputs, TPU I/Os, TMR I/Os, SCI I/Os and interrupt inputs EDACK3 PO5-B/ TIOCB4-B/ TMO1-B/ SCK3 TIOCB4-B P84/IRQ4-B/EDACK2 P84/IRQ4-B IRQ4-B P83/IRQ3
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports Mode 3, 7 Port Description Mode 1 Port B General I/O port also A15 functioning as address outputs and TPU I/Os Mode 2 Mode 4 PB7/A15 EXPE = 1 EXPE = 0 Open Pull-up MOS Capability Drain Output Capability 5-V Ο All output ⎯ TCLKH TCLKH TIOCA8 A14 PB6/A14 PB6/TIOCA8 A13 PB5/A13 PB5/TIOCB7/ TIOCB7/ TCLKG TCLKG A12 PB4/A12 PB4/TIOCA7 TIOCA7 A11 PB3/A11 PB3/TIOCD6/ TIOCD6/ Tolerance pin functions other than address outpu
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports Mode 3, 7 Port Description Mode 1 Port F General I/O port also PF7/φ PF7/φ PF6/AS/AH PF6 functioning as interrupt inputs, bus control signal I/Os, SSU I/Os, and A/D converter inputs Mode 2 Mode 4 EXPE = 1 EXPE = 0 Schmitt- Input Open triggered input Pin*2 Pull-up MOS Capability Drain Output Capability 5-V ⎯ ⎯ ⎯ ⎯ Tolerance All output pin functions other than AS and AH RD All output PF5 pin functions other than RD HWR P
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports Mode 3, 7 Port Description Port G General I/O port also functioning as bus control signal I/Os Mode 1 Mode 2 PG6/BREQ-A Mode 4 EXPE = 1 EXPE = 0 PG6 Schmitt- Input Open triggered input Pin*2 Pull-up MOS Capability Drain Output Capability 5-V ⎯ ⎯ All output ⎯ Tolerance pin functions PG5/BACK-A PG5 All output pin functions other than BACK-A PG4/BREQO-A PG4 All output pin functions other than BREQO-A PG3/CS3/RAS3/CAS*1 PG3
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports Mode 3, 7 Port Description Port H General I/O port also functioning as interrupt inputs and bus control signal I/Os Mode 1 Mode 2 Mode 4 PH3/CS7/OE-A/CKE-A*1/IRQ7-B EXPE = 1 EXPE = 0 PH3/IRQ7-B Schmitt- Input Open triggered input Pin*2 Pull-up MOS Capability Drain Output Capability 5-V IRQ7-B ⎯ All output ⎯ Tolerance pin functions other than CS7, OEA and CKE-A*1 PH2/CS6/IRQ6-B PH2/IRQ6-B IRQ6-B All output pin functions other
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports Table 10.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports Input Mode 3, 7 Schmitt- 5-V ⎯ ⎯ ⎯ ⎯ All output pin functions ⎯ Description Mode 1 Port 4 General I/O port also P47/IRQ7-B/AN7_0 IRQ7-B functioning as A/D converter analog inputs and interrupt inputs P46/IRQ6-B/AN6_0 IRQ6-B P45/IRQ5-B/AN5_0 IRQ5-B P44/IRQ4-B/AN4_0 IRQ4-B P43/IRQ3-B/AN3_0 IRQ3-B P42/IRQ2-B/AN2_0 IRQ2-B P41/IRQ1-B/AN1_0 IRQ1-B General I/O port also functioning as interrupt inputs, A/D converter inputs, SCI
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports Input Mode 3, 7 SchmittPort Description Mode 1 Port A General I/O port also PA7/A23/CS7/IRQ7-A/ PA7/A23/CS7/IRQ7-A/ functioning as address outputs, interrupt inputs, SSU I/Os, SCI I/Os, and bus control signal outputs SSO0-B SSO0-B PA7/IRQ7-A/ IRQ7-A SSO0-B PA6/A22/IRQ6-A/ SSI0-B PA6/A22/IRQ6-A/ SSI0-B PA6/IRQ6-A/ IRQ6-A SSI0-B PA5/A21/IRQ5-A/ PA5/A21/IRQ5-A/ PA5/IRQ5-A/ IRQ5-A SSCK0-B SSCK0-B SSCK0-B A20/IRQ4-A PA4/A20/IRQ4-A/
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports Input Mode 3, 7 SchmittPort Description Port D General I/O port also functioning as data I/Os and address outputs Port E General I/O port also functioning as data I/Os and address outputs Page 520 of 1408 Open Drain Output Capability 5-V EXPE = 0 Pull-up triggered MOS input Pin* Capability D15/AD15 PD7 ⎯ All output ⎯ D14/AD14 PD6 D13/AD13 PD5 D12/AD12 PD4 D11/AD11 PD3 D10/AD10 PD2 D9/AD9 PD1 D8/AD8 PD0 PE7/D7/AD7 PE7
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports Input Mode 3, 7 SchmittMode 4 5-V EXPE = 0 Drain Output Capability ⎯ ⎯ ⎯ Port Description Mode 1 Port F General I/O port also PF7/φ PF7/φ PF6/AS/AH PF6 functioning as bus control signal I/Os, SSU I/Os, and A/D converter inputs Mode 2 EXPE = 1 Open Pull-up triggered MOS input Pin* Capability ⎯ Tolerance All output pin functions other than AS and AH RD PF5 All output pin functions other than RD HWR PF4 All output pin funct
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports Input Mode 3, 7 SchmittPort Description Port G General I/O port also functioning as bus control signal I/Os Mode 1 Mode 2 PG6/BREQ-A Mode 4 EXPE = 1 Open Drain Output Capability 5-V EXPE = 0 Pull-up triggered MOS input Pin* Capability PG6 ⎯ All output ⎯ ⎯ Tolerance pin functions PG5/BACK-A PG5 All output pin functions other than BACK-A PG4/BREQO-A/CS4 PG4 All output pin functions other than BREQO-A and CS4 PG3/CS3/RAS3 All
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H8S/2456, H8S/2456R, H8S/2454 Group 10.1 Section 10 I/O Ports Port 1 Port 1 is an 8-bit I/O port that also has other functions. Port 1 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. • • • • • Port 1 data direction register (P1DDR) Port 1 data register (P1DR) Port 1 register (PORT1) Port 1 open drain control register (P1ODR) Port function control register 5 (PFCR5) 10.1.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.1.2 Port 1 Data Register (P1DR) P1DR stores output data for the port 1 pins. Bit Bit Name Initial Value R/W Description 7 P17DR 0 R/W 6 P16DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 5 P15DR 0 R/W 4 P14DR 0 R/W 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0 P10DR 0 R/W 10.1.3 Port 1 Register (PORT1) PORT1 shows the pin states of port 1.
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H8S/2456, H8S/2456R, H8S/2454 Group 10.1.4 Section 10 I/O Ports Port 1 Open Drain Control Register (P1ODR) P1ODR specifies the output type of each port 1 pin. Bit Bit Name Initial Value R/W Description 7 P17ODR 0 R/W 6 P16ODR 0 R/W 5 P15ODR 0 R/W Setting a P1ODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a P1ODR bit to 0 makes the corresponding pin a CMOS output pin.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.1.5 Pin Functions Port 1 pins also function as the pins for PPG outputs, TPU I/Os, EXDMAC I/Os (H8S/2456 group, H8S/2456R group), SSU I/Os, and DMAC I/Os (H8S/2454 group). The correspondence between the register specification and the pin functions is shown below.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • Modes 3 and 7 (EXPE = 0) SSU settings (1) in table below (2) in table (4) in table (3) in table below below below 0 ⎯ EDRAKE TPU channel 2 settings (1) in table below ⎯ (2) in table below P17DDR ⎯ 0 1 1 NDER15 ⎯ ⎯ 0 1 TIOCB2 output P17 input P17 output PO15 output Pin function TIOCB2 input* 0*6 0*6 ⎯ ⎯ SCS0-A input*3*7 SCS0-A I/O*5*7 SCS0-A output*4*7 1 TCLKD input* 2 Notes: 1.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports SSU settings (2) (1) (2) SSUMS (4) (1) 0 1 MSS 0 CSS1 x CSS0 x 0 1 SCS input ⎯ SCS input Pin state (3) 1 x 0 1 0 x 1 x Automatic SCS SCS output I/O ⎯ [Legend] x: Don't care ⎯: Not used as the SSU pin (can be used as an I/O port). Note: See tables 20.4 to 20.6.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • Modes 3 and 7 (EXPE = 0) SSU settings (1) in table below EDRAKE TPU channel 2 settings (2) in table below ⎯ 0 (1) in table below ⎯ (2) in table below P16DDR ⎯ 0 1 1 NDER14 ⎯ ⎯ 0 1 TIOCA2 output P16 input P16 output PO14 output Pin function TIOCA2 input* TPU channel 2 settings MD3 to MD0 IOA3 to IOA0 (2) (1) B'0000, B'01xx (3) in table below ⎯ (1) B'001x B'0010 B'0001 to B'0011, B'0101 to B'0111 B'xx00 CCLR1, CCLR0
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports SSU settings (1) (2) SSUMS (1) (3) (1) (2) (1) 0 MSS (3) 1 0 1 0 1 SCKS 0 1 0 1 0 1 0 1 Pin state ⎯ SSCK input ⎯ SSCK output ⎯ SSCK input ⎯ SSCK output [Legend] ⎯: Not used as the SSU pin (can be used as an I/O port). Note: See tables 20.4 to 20.6.
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H8S/2456, H8S/2456R, H8S/2454 Group TPU channel 1 settings Section 10 I/O Ports (2) MD3 to MD0 (1) (2) B'0000, B'01xx (2) (1) B'0010 (2) B'0011 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 ⎯ B'xx00 CCLR1, CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'10 B'10 Output function ⎯ Output compare output ⎯ ⎯ PWM mode 2 output ⎯ IOB3 to IOB0 Other than B'xx00 [Legend] x: Don't care SSU (1) (1) (3) (3) (2) (1) (2) (1) (1) (1) (1) (2) (1) (2) (2) (1) (2) settings SSUMS 0
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • P14/PO12/TIOCA1/SSO0-A The pin function is switched as shown below according to the combination of TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOA3 to IOA0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bit NDER12 in NDERH of PPG, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of SSU, bits SSO0S1 and SSO0S0 in PFCR5, and bit P14DDR.
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H8S/2456, H8S/2456R, H8S/2454 Group SSU (1) (2) (1) (2) (1) Section 10 I/O Ports (3) (3) (2) (3) (2) (3) (1) (3) (3) (1) (3) (3) settings SSUMS 0 0 BIDE 0 1* MSS 2 0 TE 1 0 1 1* 0 0 0 1 0 1 1 1 0 0 1 0 1 1 0 1 RE 0 1 0 1 1 0 1 1 0 1 0 1 0 1 1 0 1 Pin ⎯ SSO ⎯ SSO ⎯ SSO SSO SSO SSO SSO SSO ⎯ SSO SSO ⎯ SSO SSO output output input output output state input input output input output output output [Legend] ⎯: Not used as t
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports TPU channel 0 settings (2) MD3 to MD0 (1) B'0000 (2) (2) (1) B'0010 (2) B'0011 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 ⎯ B'xx00 CCLR2 to CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'110 B'110 Output function ⎯ Output compare output ⎯ ⎯ PWM mode 2 output ⎯ IOD3 to IOD0 Other than B'xx00 [Legend] x: Don't care • P12/PO10/TIOCC0/TCLKA The pin function is switched as shown below according to the combination of the TPU chan
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H8S/2456, H8S/2456R, H8S/2454 Group TPU channel 0 settings (2) MD3 to MD0 IOC3 to IOC0 Section 10 I/O Ports (1) B'0000 (2) (1) (1) B'001x B'0010 B'0011 Other than B'xx00 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR2 to CCLR0 ⎯ ⎯ ⎯ ⎯ Output function ⎯ Output compare output ⎯ (2) Other than B'101 B'101 ⎯ PWM*3 mode PWM mode 1 output 2 output [Legend] x: Don't care Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports TPU channel 0 settings (2) MD3 to MD0 (1) B'0000 (2) (2) (1) B'0010 (2) B'0011 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 ⎯ B'xx00 CCLR2 to CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'010 B'010 Output function ⎯ Output compare output ⎯ ⎯ PWM mode 2 output ⎯ IOB3 to IOB0 Other than B'xx00 [Legend] x: Don't care • P10/PO8/TIOCA0 The pin function is switched as shown below according to the combination of the TPU channel 0 s
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H8S/2456, H8S/2456R, H8S/2454 Group TPU channel 0 settings (2) MD3 to MD0 IOA3 to IOA0 Section 10 I/O Ports (1) B'0000 (2) (1) (1) (2) B'001x B'0010 B'0011 Other than B'xx00 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR2 to CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'001 B'001 Output function ⎯ Output compare output ⎯ PWM*2 mode 1 output PWM mode 2 output ⎯ [Legend] x: Don't care Notes: 1.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports (2) Pin Functions of H8S/2454 Group • P17/PO15/TIOCB2/TCLKD/SCS0-A The pin function is switched as shown below according to the combination of the TPU channel 2 settings (by bits MD3 to MD0 in TMDR_2, bits IOB3 to IOB0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2), bits TPSC2 to TPSC0 in TCR_0 and TCR_5, bit NDER15 in NDERH of PPG, bits MSS, CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of SSU, bits SCS0S1 and SCS0S0 in PFCR5, and bit P17DDR.
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H8S/2456, H8S/2456R, H8S/2454 Group TPU channel 2 settings MD3 to MD0 (2) Section 10 I/O Ports (1) (2) B'0000, B'01xx (2) (1) B'0010 (2) B'0011 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 ⎯ B'xx00 CCLR1, CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'10 B'10 Output function ⎯ Output compare output ⎯ ⎯ PWM mode 2 output ⎯ (2) (1) (3) (1) IOB3 to IOB0 Other than B'xx00 [Legend] x: Don't care SSU settings (2) SSUMS (4) 0 1 MSS 0 CSS1 x CSS0 x 0 1 0 1 x SCS input
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • P16/PO14/TIOCA2/SSCK0-A The pin function is switched as shown below according to the combination of the TPU channel 2 settings (by bits MD3 to MD0 in TMDR_2, bits IOA3 to IOA0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2), bit NDER14 in NDERH of PPG, bits MSS and SCKS in SSCRH and bit SSUMS in SSCRL of SSU, bits SSCK0S1 and SSCK0S0 in PFCR5, and bit P16DDR.
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H8S/2456, H8S/2456R, H8S/2454 Group SSU settings (1) Section 10 I/O Ports (2) (1) SSUMS (3) (1) (2) (1) 0 MSS (3) 1 0 1 0 1 SCKS 0 1 0 1 0 1 0 1 Pin state ⎯ SSCK input ⎯ SSCK output ⎯ SSCK input ⎯ SSCK output [Legend] ⎯: Not used as the SSU pin (can be used as an I/O port). Note: See tables 20.4 to 20.6.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports TPU channel 1 settings (2) MD3 to MD0 (1) (2) B'0000, B'01xx (2) (1) B'0010 (2) B'0011 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 ⎯ B'xx00 CCLR1, CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'10 B'10 Output function ⎯ Output compare output ⎯ ⎯ PWM mode 2 output ⎯ IOB3 to IOB0 Other than B'xx00 [Legend] x: Don't care SSU (1) (1) (3) (3) (2) (1) (2) (1) (1) (1) (1) (2) (1) (2) (2) (1) (2) settings SSUMS 0
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • P14/DACK0/PO12/TIOCA1/SSO0-A The pin function is switched as shown below according to the combination of bit SAE0 in DMABCRH of DMAC, TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOA3 to IOA0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bit NDER12 in NDERH of PPG, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of SSU, bits SSO0S1 and SSO0S0 in PFCR5, and bit P14DDR.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports SSU (1) (2) (1) (2) (1) (3) (3) (2) (3) (2) (3) (1) (3) (3) (1) (3) (3) settings SSUMS 0 0 BIDE 0 1* MSS 0 TE 1 0 1 0 1 1* 2 0 0 1 1 0 1 0 0 1 1 0 1 0 1 RE 0 1 0 1 1 0 1 1 0 1 0 1 0 1 1 0 1 Pin state ⎯ SSO ⎯ SSO ⎯ SSO SSO SSO SSO SSO SSO ⎯ SSO SSO ⎯ SSO SSO input output output output input input output output input output output output [Legend] ⎯: Not used as t
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H8S/2456, H8S/2456R, H8S/2454 Group TPU channel 0 settings Section 10 I/O Ports (2) MD3 to MD0 (1) (2) B'0000 (2) (1) B'0010 (2) B'0011 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 ⎯ B'xx00 CCLR2 to CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'110 B'110 Output function ⎯ Output compare output ⎯ ⎯ PWM mode 2 output ⎯ IOD3 to IOD0 Other than B'xx00 [Legend] x: Don't care • P12/TEND0/PO10/TIOCC0/TCLKA The pin function is switched as shown below according to the combination of bit T
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports TPU channel 0 settings (2) MD3 to MD0 IOC3 to IOC0 (1) B'0000 (2) (1) (1) B'001x B'0010 B'0011 Other than B'xx00 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR2 to CCLR0 ⎯ ⎯ ⎯ ⎯ Output function ⎯ Output compare output ⎯ (2) Other than B'101 B'101 ⎯ PWM*3 mode PWM mode 1 output 2 output [Legend] x: Don't care Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx.
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H8S/2456, H8S/2456R, H8S/2454 Group TPU channel 0 settings Section 10 I/O Ports (2) MD3 to MD0 (1) B'0000 (2) (2) (1) B'0010 (2) B'0011 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 ⎯ B'xx00 CCLR2 to CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'010 B'010 Output function ⎯ Output compare output ⎯ ⎯ PWM mode 2 output ⎯ IOB3 to IOB0 Other than B'xx00 [Legend] x: Don't care • P10/DREQ0/PO8/TIOCA0 The pin function is switched as shown below according to the combination of the TPU chann
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports TPU channel 0 settings (2) MD3 to MD0 IOA3 to IOA0 (1) B'0000 (2) (1) B'001x B'0010 B'0011 Other than B'xx00 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR2 to CCLR0 ⎯ ⎯ ⎯ ⎯ Output function ⎯ Output compare output ⎯ (1) (2) Other than B'001 PWM*2 mode PWM mode 1 output 2 output B'001 ⎯ [Legend] x: Don't care Notes: 1. TIOCA0 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx.
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H8S/2456, H8S/2456R, H8S/2454 Group 10.2 Section 10 I/O Ports Port 2 Port 2 is an 8-bit I/O port that also has other functions. Port 2 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. • • • • • Port 2 data direction register (P2DDR) Port 2 data register (P2DR) Port 2 register (PORT2) Port 2 open drain control register (P2ODR) Port function control register 3 (PFCR3) 10.2.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.2.2 Port 2 Data Register (P2DR) P2DR stores output data for the port 2 pins. Bit Bit Name Initial Value R/W Description 7 P27DR 0 R/W 6 P26DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 5 P25DR 0 R/W 4 ⎯ 0 ⎯ Bits 4 to 1 are reserved. 3 ⎯ 0 ⎯ 2 ⎯ 0 ⎯ These bits are read as 0. When written, the initial value should be written to.
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H8S/2456, H8S/2456R, H8S/2454 Group 10.2.4 Section 10 I/O Ports Port 2 Open Drain Control Register (P2ODR) P2ODR specifies the output type of each port 2 pin. Bit Bit Name Initial Value R/W Description 7 P27ODR 0 R/W 6 P26ODR 0 R/W 5 P25ODR 0 R/W Setting a P2ODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a P2ODR bit to 0 makes the corresponding pin a CMOS output pin. 4 ⎯ 0 ⎯ Bits 4 to 1 are reserved.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.2.5 Pin Functions Port 2 pins also function as the pins for PPG outputs, TPU I/Os, interrupt inputs (H8S/2456 group, H8S/2456R group), 8-bit timer I/Os (H8S/2454 group), I2C I/Os, USB I/Os, and bus control signal inputs. The correspondence between the register specification and the pin functions is shown below.
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H8S/2456, H8S/2456R, H8S/2454 Group TPU channel 5 settings (2) MD3 to MD0 Section 10 I/O Ports (1) (2) B'0000, B'01xx (2) (1) B'0010 (2) B'0011 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 ⎯ B'xx00 CCLR1, CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'10 B'10 Output function ⎯ Output compare output ⎯ ⎯ PWM mode 2 output ⎯ IOB3 to IOB0 Other than B'xx00 [Legend] x: Don't care • P26/PO6/TIOCA5/IRQ14-B/SDA2/ADTRG1 The pin function is switched as shown below according to the combinati
PAGE 584
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports TPU channel 5 settings MD3 to MD0 IOA3 to IOA0 (2) (1) B'0000, B'01xx (2) (1) B'001x B'0010 B'0011 Other than B'xx00 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR1, CCLR0 ⎯ ⎯ ⎯ ⎯ Output function ⎯ Output compare output ⎯ (1) (2) Other than B'01 PWM*3 mode PWM mode 1 output 2 output B'01 ⎯ [Legend] x: Don't care Notes: 1. TIOCA5 input when MD3 to MD0 = B'0000 or B'01×× and IOA3 = 1.
PAGE 585
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • P25/PO5-A/TIOCB4-A/IRQ13-B/WAIT-B/VBUS The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit WAITE in BCR of the bus controller, TPU channel 4 settings by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4, bit NDER5 in NDERL of PPG, bits PPGS and TPUS in PFCR3, bit WAITS in PFCR4, bit P25DDR, and bit ITS13 in ITSR of the interrupt controller.
PAGE 586
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports TPU channel 4 settings MD3 to MD0 (2) (1) (2) B'0000, B'01xx (2) (1) B'0010 (2) B'0011 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 ⎯ B'xx00 CCLR1, CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'10 B'10 Output function ⎯ Output compare output ⎯ ⎯ PWM mode 2 output ⎯ IOB3 to IOB0 Other than B'xx00 [Legend] x: Don't care • P20/PO0-A/TIOCA3-A/IRQ8-B/PUPD+ The pin function is switched as shown below according to the combination
PAGE 587
H8S/2456, H8S/2456R, H8S/2454 Group TPU channel 3 settings (2) MD3 to MD0 IOA3 to IOA0 Section 10 I/O Ports (1) B'0000 (2) (1) B'001x B'0010 B'0011 Other than B'xx00 B'0000, B'0100, B'1xxx B'0001 to B'0011 B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR2 to CCLR0 ⎯ ⎯ ⎯ ⎯ Output function ⎯ Output compare output ⎯ (1) (2) Other than B'001 PWM*3 mode PWM mode 2 1 output output B'001 ⎯ [Legend] x: Don't care Notes: 1. TIOCA3-A input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports (2) Pin Functions of H8S/2454 Group • P27/PO7/TIOCB5/SCL2 The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR_5, bits IOB3 to IOB0 in TIOR_5, and bits CCLR1 and CCLR0 in TCR_5), bit NDER7 in NDERL of PPG, bit ICE in ICCRA_2 of I2C, and bit P27DDR.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • P26/PO6/TIOCA5/SDA2/ADTRG1 The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR_5, bits IOA3 to IOA0 in TIOR_5, and bits CCLR1 and CCLR0 in TCR_5), bit NDER6 in NDERL of PPG, bits TRGS1, TRGS0, and EXTRGS in ADCR_1 of ADC, bit ICE in ICCRA_2 of I2C, and bit P26DDR.
PAGE 590
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • P25/WAIT-B/PO5-A/TIOCB4-A/TMO1-A/VBUS The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit WAITE in BCR of the bus controller, TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bits OS3 to OS0 in TCSR_1 of the 8-bit timer, bit NDER5 in NDERL of PPG, bits PPGS, TPUS, and TMRS in PFCR3, bit WAITS in PFCR4, and bit P25DDR.
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H8S/2456, H8S/2456R, H8S/2454 Group TPU channel 4 settings MD3 to MD0 (2) Section 10 I/O Ports (1) (2) B'0000, B'01xx (2) (1) B'0010 (2) B'0011 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 ⎯ B'xx00 CCLR1, CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'10 B'10 Output function ⎯ Output compare output ⎯ ⎯ PWM mode 2 output ⎯ IOB3 to IOB0 Other than B'xx00 [Legend] x: Don't care • P20/PO0-A/TIOCA3-A/TMRI0-A/PUPD+ The pin function is switched as shown below according to the combination
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports TPU channel 3 settings (2) MD3 to MD0 IOA3 to IOA0 (1) B'0000 (2) (1) B'001x B'0010 B'0011 Other than B'xx00 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR2 to CCLR0 ⎯ ⎯ ⎯ ⎯ Output function ⎯ Output compare output ⎯ (1) (2) Other than B'001 PWM*3 mode PWM mode 2 1 output output B'001 ⎯ [Legend] x: Don't care Notes: 1.
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H8S/2456, H8S/2456R, H8S/2454 Group 10.3 Section 10 I/O Ports Port 3 Port 3 is a 6-bit I/O port that also has other functions. Port 3 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. • • • • • Port 3 data direction register (P3DDR) Port 3 data register (P3DR) Port 3 register (PORT3) Port 3 open drain control register (P3ODR) Port function control register 2 (PFCR2) 10.3.
PAGE 594
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.3.2 Port 3 Data Register (P3DR) P3DR stores output data for the port 3 pins. Bit Bit Name Initial Value R/W Description 7, 6 ⎯ All 0 ⎯ Reserved These bits are always read as 0 and cannot be modified. 5 P35DR 0 R/W 4 P34DR 0 R/W 3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W 0 P30DR 0 R/W 10.3.3 Output data for a pin is stored when the pin function is specified as a general purpose I/O.
PAGE 595
H8S/2456, H8S/2456R, H8S/2454 Group 10.3.4 Section 10 I/O Ports Port 3 Open Drain Control Register (P3ODR) P3ODR specifies the output type of each port 3 pin. Bit Bit Name Initial Value R/W Description 7, 6 ⎯ All 0 ⎯ Reserved These bits are always read as 0. Only the initial values should be written to these bits.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.3.5 Pin Functions Port 3 pins also function as the pins for SCI I/Os, I2C I/Os, and bus control signal outputs. The correspondence between the register specification and the pin functions is shown below.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • Modes 3 and 7 (EXPE = 0) OEE ⎯ OES ⎯ RMTS2 to RMTS0 ⎯ ICE 0 CKE1 C/A ⎯ 1 ⎯ ⎯ 1 ⎯ ⎯ ⎯ 0 CKE0 0 0 1 ⎯ ⎯ ⎯ ⎯ P35 input P35 output SCK1 output SCK1 output SCK1 input SCL0 I/O*1 P35DDR Pin function 1 1 0 Notes: 1. NMOS open-drain output regardless of P35ODR. 2. Not supported in the H8S/2456 Group and H8S/2454 Group.
PAGE 598
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • P33/RxD1/SCL1 The pin function is switched as shown below according to the combination of bit ICE in ICCRA_1 of I2C, bit RE in SCR_1 of SCI, and bit P33DDR. ICE 0 RE P33DDR Pin function 1 0 1 ⎯ 0 1 ⎯ ⎯ P33 input P33 output RxD1 input SCL1 I/O* Note: NMOS open-drain output regardless of P33ODR.
PAGE 599
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • P30/TxD0/IrTxD The pin function is switched as shown below according to the combination of bit TE in SCR_0 of SCI and bit P30DDR. TE P30DDR Pin function R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.4 Port 4 Port 4 is an 8-bit input-only port that also has other functions, such as analog input pins. Port 4 has the following register. • Port 4 register (PORT4) 10.4.1 Port 4 Register (PORT4) PORT4 is an 8-bit read-only register that shows the pin states of port 4. PORT4 cannot be modified. Bit Bit Name Initial Value R/W Description 7 P47 ⎯* R The pin states are always read from this register.
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H8S/2456, H8S/2456R, H8S/2454 Group (2) Section 10 I/O Ports Pin Functions of H8S/2454 Group • P47/IRQ7-B/AN7_0 Pin function AN7_0 input IRQ7-B interrupt input* • P46/IRQ6-B/AN6_0 Pin function AN6_0 input IRQ6-B interrupt input* • P45/IRQ5-B/AN5_0 Pin function AN5_0 input IRQ5-B interrupt input* • P44/IRQ4-B/AN4_0 Pin function AN4_0 input IRQ4-B interrupt input* • P43/IRQ3-B/AN3_0 Pin function AN3_0 input IRQ3-B interrupt input* • P42/IRQ2-B/AN2_0 Pin function AN2_0 input IRQ2-B interrupt inp
PAGE 602
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.5 Port 5 Port 5 is a 4-bit I/O port. Port 5 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. • • • • • Port 5 data direction register (P5DDR) Port 5 data register (P5DR) Port 5 register (PORT5) Port 5 open drain control register (P5ODR) Port function control register 4 (PFCR4) 10.5.
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H8S/2456, H8S/2456R, H8S/2454 Group 10.5.3 Section 10 I/O Ports Port 5 Register (PORT5) PORT5 shows the pin states of port 5. PORT5 cannot be modified. Bit Bit Name Initial Value R/W Description 7 to 4 ⎯ Undefined R Reserved If these bits are read, they will return an undefined value. 3 P53 ⎯* R 2 P52 ⎯* R 1 P51 ⎯* R 0 P50 ⎯* R Note: * 10.5.4 If the P53 to P50 bits are read while a P5DDR bit is set to 1, the corresponding P5DR value is read.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.5.5 Pin Functions Port 5 pins also function as the pins for SCI I/Os, A/D converter inputs, interrupt inputs, I2C I/Os, bus control signal I/Os, PPG outputs, TPU I/Os, and 8-bit timer I/Os. The correspondence between the register specification and the pin functions is shown below.
PAGE 605
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • P52/SCK2/IRQ2-A/BACK-B/PO4-B/TIOCA4-B/TMO0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit BRLE in BCR of the bus controller, bits OS3 to OS0 in TCSR0 of 8-bit timer, bits MD3 to MD0 in TMDR_4 of TPU, bits IOA3 to IOA0 in TIOR_4, TPU channel 4 settings by bits CCLR1 and CCLR0 in TCR_4, bit NDER4 in NDERL of PPG, bit C/A in SMR_2 and bits CKE0 and CKE1 in SCR_2 of SCI, bits PPGS, TPUS,
PAGE 606
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • Modes 3 and 7 (EXPE = 0) ⎯ BRLE BACKS TPU channel 4 settings (1) in table below (2) in table below OS3 to OS0 ⎯ CKE1 ⎯ C/A ⎯ CKE0 ⎯ P52DDR ⎯ 0 1 NDER4 ⎯ ⎯ 0 TIOCA4-B 5 output* P52 input P52 output Pin function All 0 Not all 0 1 ⎯ 1 ⎯ ⎯ 1 ⎯ ⎯ ⎯ 1 ⎯ ⎯ ⎯ ⎯ 1 ⎯ ⎯ ⎯ ⎯ PO4-B 4 output* SCK2 output SCK2 output SCK2 input TMO0-B 6 output* 0 0 0 TIOCA4-B input*1*5 IRQ2-A interrupt input*2 TPU channel 4 setti
PAGE 607
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • P51/RxD2/IRQ1-A/SCL3/BREQ-B/PO2-B/TIOCC3-B/TMCI0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit BRLE in BCR of the bus controller, bit ICE in ICCRA_3 of the I 2 C, bits MD3 to MD0 in TMDR_3 of TPU, bits IOC3 to IOC0 in TIORL_3, TPU channel 3 settings by bits CCLR2 to CCLR0 in TCR_3, bit NDER2 in NDERL of PPG, bit RE in SCR_2 of the SCI, bit P51DDR, bits PPGS, TPUS, and TMRS in PFCR3,
PAGE 608
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • Modes 3 and 7 (EXPE = 0) ⎯ BRLE BREQS ICE TPU channel 3 settings 0 (1) in table below ⎯ (2) in table below RE ⎯ P51DDR ⎯ 0 1 NDER2 ⎯ ⎯ TIOCC3-B output*7 P51 input Pin function 1 1 ⎯ 1 ⎯ ⎯ 0 1 ⎯ ⎯ P51 output PO2-B output*6 RxD2 input SCL3 I/O 0 1 7 TIOCC3-B input* * IRQ1-A interrupt input*2 3 8 TMCI0-B input* * Page 578 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group TPU channel 3 settings (2) MD3 to MD0 IOC3 to IOC0 Section 10 I/O Ports (1) B'0000 (2) (1) B'001x B'0010 B'0011 Other than B'xx00 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR2 to CCLR0 ⎯ ⎯ ⎯ ⎯ Output function ⎯ Output compare output ⎯ (1) (2) Other than B'101 PWM*4 mode PWM mode 1 output 2 output B'101 ⎯ Notes: 1. TIOCC3-B input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx. 2.
PAGE 610
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • P50/TxD2/IRQ0-A/SDA3/BREQO-B/PO0-B/TIOCA3-B/TMRI0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit BRLE of the bus controller, bit BREQOE, bit ICE in ICCRA_3 of the I2C, bits MD3 to MD0 in TMDR_3 of TPU, bits IOA3 to IOA0 in TIORH_3, TPU channel 3 settings by bits CCLR2 to CCLR0 in TCR_3, bit NDER0 in NDERL of PPG, bit TE in SCR_2 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, bit BRE
PAGE 611
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • Modes 3 and 7 (EXPE = 0) BRLE ⎯ BREQOE ⎯ BREQOS ⎯ ICE TPU channel 3 settings 0 (1) in table below 1 TE ⎯ P50DDR ⎯ 0 1 1 NDER0 ⎯ ⎯ 0 1 Pin function ⎯ (2) in table below 0 TIOCA3-B 7 output* 1 ⎯ ⎯ ⎯ ⎯ ⎯ 6 P50 input P50 output PO0-B output* TxD2 output SDA3*5 I/O TIOCA3-B input*1*7 IRQ0-A interrupt input*2 3 8 TMRI0-B input* * TPU channel 3 settings (2) MD3 to MD0 IOA3 to IOA0 (1) B'0000 (2) (1) B'001x B'0010
PAGE 612
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.6 Port 6 Note: Port 6 is not supported in the H8S/2454 Group. Port 6 is a 6-bit I/O port that also has other functions. Port 6 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. • • • • • Port 6 data direction register (P6DDR) Port 6 data register (P6DR) Port 6 register (PORT6) Port 6 open drain control register (P6ODR) Port function control register 3 (PFCR3) 10.6.
PAGE 613
H8S/2456, H8S/2456R, H8S/2454 Group 10.6.2 Section 10 I/O Ports Port 6 Data Register (P6DR) P6DR stores output data for the port 6 pins. Bit Bit Name Initial Value R/W Description 7, 6 ⎯ All 0 ⎯ Reserved These bits are always read as 0 and cannot be modified. 5 P65DR 0 R/W 4 P64DR 0 R/W 3 P63DR 0 R/W 2 P62DR 0 R/W 1 P61DR 0 R/W 0 P60DR 0 R/W 10.6.3 Output data for a pin is stored when the pin function is specified as a general purpose I/O.
PAGE 614
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.6.4 Port 6 Open Drain Control Register (P6ODR) P6ODR specifies the output type of each port 6 pin. Bit Bit Name Initial Value R/W Description 7, 6 ⎯ All 0 ⎯ Reserved These bits are always read as 0. Only the initial values should be written to these bits. 5 P65ODR 0 R/W 4 P64ODR 0 R/W 3 P63ODR 0 R/W 2 P62ODR 0 R/W 1 P61ODR 0 R/W 0 P60ODR 0 R/W 10.6.
PAGE 615
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • P64/IRQ12-A/DACK0/TMO0-A The pin function is switched as shown below according to the combination of bit SAE0 in DMABCRH of DMAC, bits OS3 to OS0 in TCSR_0 of the 8-bit timer, bit TMRS in PFCR3, bit P64DDR, and bit ITS12 in ITSR of the interrupt controller. SAE0 0 OS3 to OS0 All 0 P64DDR Pin function 1 0 ⎯ 1 P64 input ⎯ Not all 0 P64 output TMO0-A output* ⎯ DACK0 output 2 IRQ12-A interrupt input* 1 Notes: 1.
PAGE 616
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • P62/IRQ10-A/TEND0/TMCI0-A The pin function is switched as shown below according to the combination of bit TEE0 in DMATCR of DMAC, bit TMRS in PFCR3, bit P62DDR, and bit ITS10 in ITSR of the interrupt controller. TEE0 P62DDR Pin function 0 1 0 1 P62 input P62 output ⎯ TEND0 output IRQ10-A interrupt input* 2 1 3 TMCI0-A input* * Notes: 1. IRQ10-A input when the ITS10 bit in ITSR is 0. 2.
PAGE 617
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • P60/IRQ8-A/DREQ0/TMRI0-A The pin function is switched as shown below according to the combination of bits TMRS and USBDRQE in PFCR3, bit P60DDR, and bit ITS8 in ITSR of the interrupt controller. P60DDR Pin function 0 1 P60 input P60 output 1 3. TMRI0-A input* * DREQ0 input*4 IRQ8-A interrupt input* 2 Notes: 1.
PAGE 618
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.7 Port 8 Port 8 is a 6-bit I/O port that also has other functions. Port 8 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. • • • • • Port 8 data direction register (P8DDR) Port 8 data register (P8DR) Port 8 register (PORT8) Port 8 open drain control register (P8ODR) Port function control register 3 (PFCR3) 10.7.
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H8S/2456, H8S/2456R, H8S/2454 Group 10.7.2 Section 10 I/O Ports Port 8 Data Register (P8DR) P8DR stores output data for the port 8 pins. Bit Bit Name Initial Value R/W Description 7, 6 ⎯ All 0 ⎯ Reserved These bits are always read as 0 and cannot be modified. 5 P85DR 0 R/W 4 P84DR 0 R/W 3 P83DR 0 R/W 2 P82DR 0 R/W 1 P81DR 0 R/W 0 P80DR 0 R/W 10.7.3 Output data for a pin is stored when the pin function is specified as a general purpose I/O.
PAGE 620
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.7.4 Port 8 Open Drain Control Register (P8ODR) P8ODR specifies the output type of each port 8 pin. Bit Bit Name Initial Value R/W Description 7, 6 ⎯ All 0 ⎯ Reserved These bits are always read as 0. Only the initial values should be written to these bits. 5 P85ODR 0 R/W 4 P84ODR 0 R/W 3 P83ODR 0 R/W 2 P82ODR 0 R/W 1 P81ODR 0 R/W 0 P80ODR 0 R/W 10.7.
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H8S/2456, H8S/2456R, H8S/2454 Group • Modes 1, 2, and 4 Section 10 I/O Ports Modes 3 and 7 (EXPE = 1) TPU channel 4 settings (1) in table below OS3 to OS0 ⎯ AMS ⎯ CKE1 ⎯ C/A ⎯ CKE0 ⎯ P85DDR ⎯ 0 1 NDER5 ⎯ ⎯ Pin function (2) in table below All 0 Not all 0 0 1 1 ⎯ ⎯ 1 ⎯ ⎯ ⎯ 1 ⎯ ⎯ ⎯ ⎯ 1 ⎯ ⎯ ⎯ ⎯ ⎯ 0 1 ⎯ ⎯ ⎯ ⎯ ⎯ P85 output PO5-B 3 output* SCK3 output SCK3 output SCK3 input 0 0 0 TIOCB4-B P85 input 4 output* ⎯ EDACK3 TMO1-B 5 output output* 2 4 TIOCB4-B
PAGE 622
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports TPU channel 4 settings MD3 to MD0 (2) (1) (2) B'0000, B'01xx (2) (1) B'0010 (2) B'0011 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 ⎯ B'xx00 CCLR1, CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'10 B'10 Output function ⎯ Output compare output ⎯ ⎯ PWM mode 2 output ⎯ IOB3 to IOB0 Other than B'xx00 [Legend] x: Don't care • P84/IRQ4-B/EDACK2 The pin function is switched as shown below according to the combination of bit AMS in E
PAGE 623
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • P83/ETEND3/IRQ3-B/RxD3/PO3-B/TIOCD3-B/TMCI1-B The pin function is switched as shown below according to the combination of bit ETENDE in EDMDR_3 of EXDMAC, bit RE in SCR_3 of SCI, TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER3 in NDERL of PPG, bits PPGS, TPUS, and TMRS in PFCR3, bit P83DDR, and bit ITS3 in ITSR of the interrupt controller.
PAGE 624
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • Modes 3 and 7 (EXPE = 0) TPU channel 3 settings (1) in table below (2) in table below ETENDE ⎯ RE ⎯ P83DDR ⎯ 0 NDER3 ⎯ ⎯ TIOCD3-B output*5 P83 input Pin function 0 1 1 ⎯ 0 1 ⎯ P83 output PO3-B output*4 0 ⎯ 1 2 RxD3 input 5 TIOCD3-B input* * IRQ3-B interrupt input*1 3 6 TMCI1-B input* * Notes: 1. IRQ3-B input when the ITS3 bit in ITSR is 1. 2. TIOCD3-B input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10xx. 3.
PAGE 625
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • P82/IRQ2-B/ETEND2 The pin function is switched as shown below according to the combination of bit ETENDE in EDMDR_2 of EXDMAC, bit P82DDR, and bit ITS2 in ITSR of the interrupt controller. Operating mode 1, 2, 4 ETENDE 3, 7 (EXPE = 1) 0 ⎯ 1 0 1 ⎯ 0 1 P82 input P82 output ETEND2 output P82 input P82 output P82DDR Pin function 3, 7 (EXPE = 0) IRQ2-B interrupt input* Note: * IRQ2-B input when the ITS2 bit in ITSR is 1.
PAGE 626
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports TPU channel 3 settings (2) MD3 to MD0 (1) B'0000 (2) (2) B'0010 (1) (2) B'0011 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 ⎯ B'xx00 CCLR2 to CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'010 B'010 Output function ⎯ Output compare output ⎯ ⎯ PWM mode 2 output ⎯ IOB3 to IOB0 Other than B'xx00 [Legend] x: Don't care • P80/IRQ0-B/EDREQ2 The pin function is switched as shown below according to the combination of bit P80DDR and b
PAGE 627
H8S/2456, H8S/2456R, H8S/2454 Group (2) Section 10 I/O Ports Pin Functions of H8S/2454 Group • P85/SCK3/PO5-B/TIOCB4-B/TMO1-B The pin function is switched as shown below according to the combination of the TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bits OS3 to OS0 in TCSR_1 of the 8-bit timer, bit NDER5 in NDERL of PPG, bit C/A in SMR_3 and bits CKE0 and CKE1 in SCR_3 of SCI, bits PPGS, TPUS, and TMRS in PFCR3, and bit P85DDR.
PAGE 628
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • P83/PO3-B/TIOCD3-B/TMCI1-B/RxD3 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER3 in NDERL of PPG, bit RE in SCR_3 of SCI, bits PPGS, TPUS, and TMRS in PFCR3, and bit P83DDR.
PAGE 629
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • P81/PO1-B/TIOCB3-B/TMRI1-B/TxD3 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER1 in NDERL of PPG, bit TE in SCR_3 of SCI, bits PPGS, TPUS, and TMRS in PFCR3, and bit P81DDR.
PAGE 630
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.8 Port 9 Port 9 is an 8-bit input-only port that also has other functions. Port 9 has the following register. • Port 9 register (PORT9) 10.8.1 Port 9 Register (PORT9) PORT9 is an 8-bit read-only register that shows the pin states of port 9. PORT9 cannot be modified. Bit Bit Name Initial Value R/W Description 7 P97 ⎯* R 6 P96 ⎯* R 5 P95 ⎯* The pin states are always read from this register.
PAGE 631
H8S/2456, H8S/2456R, H8S/2454 Group 10.8.2 Section 10 I/O Ports Pin Functions Port 9 also functions as the pins for A/D converter analog inputs and D/A converter analog outputs. The correspondence between pins is as follows.
PAGE 632
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports (2) Pin Functions of H8S/2454 Group • P95/AN13_1/DA3 Pin function AN13_1 input DA3 output • P94/AN12_1/DA2 Pin function AN12_1 input DA2 output Page 602 of 1408 R01UH0309EJ0500 Rev. 5.
PAGE 633
H8S/2456, H8S/2456R, H8S/2454 Group 10.9 Section 10 I/O Ports Port A Port A is an 8-bit I/O port that also has other functions. Port A has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers.
PAGE 634
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.9.1 Port A Data Direction Register (PADDR) The individual bits of PADDR specify input or output for the pins of port A. PADDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 PA7DDR 0 W 6 PA6DDR 0 W Pins PA4 to PA0 are address outputs.
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H8S/2456, H8S/2456R, H8S/2454 Group Bit Bit Name Initial Value Section 10 I/O Ports R/W Description • Mode 4, Modes 3 and 7 (EXPE = 1) For pins PA6 to PA0, when the corresponding bit of A22E to A16E is set to 1, setting a PADDR bit to 1 makes the corresponding pin an address output, while clearing the bit to 0 makes the corresponding pin an input port. Clearing one of bits A22E to A16E to 0 makes the corresponding pin an I/O port, and its function can be switched with PADDR.
PAGE 636
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.9.2 Port A Data Register (PADR) PADR stores output data for the port A pins. Bit Bit Name Initial Value R/W Description 7 PA7DR 0 R/W 6 PA6DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 5 PA5DR 0 R/W 4 PA4DR 0 R/W 3 PA3DR 0 R/W 2 PA2DR 0 R/W 1 PA1DR 0 R/W 0 PA0DR 0 R/W 10.9.3 Port A Register (PORTA) PORTA shows the pin states of port A.
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H8S/2456, H8S/2456R, H8S/2454 Group 10.9.4 Section 10 I/O Ports Port A Pull-Up MOS Control Register (PAPCR) PAPCR controls on/off of the input pull-up MOS for port A. Bits 7 to 5 are valid in modes 1 and 2 and all the bits are valid in modes 4 and 7. Bit Bit Name Initial Value R/W Description 7 PA7PCR 0 R/W 6 PA6PCR 0 R/W When in a input port state, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin.
PAGE 638
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.9.6 Pin Functions Port A pins also function as the pins for address outputs, interrupt inputs, SSU I/Os, SCI I/Os, and bus control signal outputs. The correspondence between the register specification and the pin functions is shown below.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • Modes 3 and 7 (EXPE = 0) ⎯ A23E 6 CS7E* 0 SSU settings (1) in table below PA7DDR 0 Pin function (2) in table below 1 PA7 input 0* ⎯ 2 PA7 output (3) in table below 4 5 SSO0-B output*3*5 SSO0-B input* * IRQ7-A interrupt input* 1 Notes: 1. IRQ7-A input when the ITS7 bit in ITSR is 0. 2. When using as SSO0-B input, set SSO0S1 and SSO0S0 in PFCR5 to B'01 before other register setting. 3.
PAGE 640
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • PA6/A22/IRQ6-A/SSI0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of SSU, bit A22E in PFCR1, bits SSO0S1 and SSO0S0 in PFCR5, bit PA6DDR, and bit ITS6 in ITSR of the interrupt controller.
PAGE 641
H8S/2456, H8S/2456R, H8S/2454 Group SSU (1) (1) (3) (3) (2) Section 10 I/O Ports (1) (2) (1) (1) (1) (1) (2) (1) (2) (2) (1) (2) settings 1 SSUMS 0 0 BIDE 0 1* MSS 2 0 TE 1 0 1 1* 0 0 0 1 0 1 1 0 0 1 0 1 1 0 1 RE 0 1 0 1 1 0 1 1 0 1 0 1 0 1 1 0 1 Pin state ⎯ ⎯ SSI SSI SSI ⎯ SSI ⎯ ⎯ ⎯ ⎯ SSI ⎯ SSI SSI ⎯ SSI input input output output input input input input [Legend] ⎯: Not used as the SSU pin (can be used as an I/O port).
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • Modes 3 and 7 EXPE 1 A21E 0 0 SSU settings PA5DDR Pin function (1) in table below 0 ⎯ 1 (2) in table below (3) in table below ⎯ ⎯ 0*4 ⎯ 0 1 1 (1) in table below 0 1 (2) in table below (3) in table below 0*4 ⎯ PA5 PA5 SSCK0-B SSCK0-B PA5 SSCK0-B SSCK0-B PA5 A21 output input output input output input output output input 2 5 *3*5 *2*5 *3*5 ** PA5 input IRQ5-A interrupt input* 1 Notes: 1.
PAGE 643
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • PA4/A20/IRQ4-A/SCS0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS, CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of SSU, bit A20E in PFCR1, bit PA4DDR, and bit ITS4 in ITSR of the interrupt controller.
PAGE 644
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports SSU settings (2) (1) (2) SSUMS (4) (3) (1) 0 1 MSS 0 CSS1 x CSS0 x 0 1 0 1 x SCS input ⎯ SCS input Automatic SCS I/O SCS output ⎯ Pin state 1 x 0 1 x [Legend] x: Don't care ⎯: Not used as the SSU pin (can be used as an I/O port). Note: See tables 20.4 to 20.6.
PAGE 645
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports Operating mode 3, 7 EXPE 0 A19E ⎯ CKE1 0 0 C/A 1 ⎯ 1 ⎯ ⎯ ⎯ ⎯ ⎯ 0 PA3DDR Pin function 0 1 1 0 1 0 CKE0 Note: 1 0 0 0 1 1 1 ⎯ ⎯ ⎯ 1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0 1 PA3 PA3 SCK4-B SCK4-B SCK4-B PA3 PA3 SCK4-B SCK4-B SCK4-B PA3 A19 input output output* output* input* input output output* output* input* input output * When using as SCK4-B input/output, set SCK4S in PFCR4 to 1 before other register setting.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • PA1/A17/TxD4-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit TE in SCR_4 of SCI, bit A17E in PFCR1, bit TXD4S in PFCR4, and bit PA1DDR.
PAGE 647
H8S/2456, H8S/2456R, H8S/2454 Group 10.9.7 Section 10 I/O Ports Port A Input Pull-Up MOS States Port A has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used by pins PA7 to PA5 in modes 1 and 2, and by all pins in modes 3, 4, and 7. The input pull-up MOS can be specified as on or off on a bit-by-bit basis. Table 10.3 summarizes the input pull-up MOS states. The input pull-up MOS should not be turned on when the SCI is used. Table 10.
PAGE 648
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.10 Port B Port B is an 8-bit I/O port that also has other functions. Port B has the following registers. • • • • • Port B data direction register (PBDDR) Port B data register (PBDR) Port B register (PORTB) Port B pull-up MOS control register (PBPCR) Port B open drain control register (PBODR) 10.10.1 Port B Data Direction Register (PBDDR) The individual bits of PBDDR specify input or output for the pins of port B.
PAGE 649
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.10.2 Port B Data Register (PBDR) PBDR stores output data for the port B pins. Bit Bit Name Initial Value R/W Description 7 PB7DR 0 R/W 6 PB6DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 5 PB5DR 0 R/W 4 PB4DR 0 R/W 3 PB3DR 0 R/W 2 PB2DR 0 R/W 1 PB1DR 0 R/W 0 PB0DR 0 R/W 10.10.3 Port B Register (PORTB) PORTB shows the pin states of port B.
PAGE 650
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.10.4 Port B Pull-Up MOS Control Register (PBPCR) PBPCR controls on/off of the input pull-up MOS for port B. PBPCR is valid in modes 4 and 7. Bit Bit Name Initial Value R/W Description 7 PB7PCR 0 R/W 6 PB6PCR 0 R/W When in a input port register state, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin.
PAGE 651
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.10.6 Pin Functions Port B pins also function as the pins for TPU I/Os and address outputs. The correspondence between the register specification and the pin functions is shown below.
PAGE 652
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • PB6/A14/TIOCA8 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 8 settings (by bits MD3 to MD0 in TMDR_8, bits IOA3 to IOA0 in TIOR_8, and bits CCLR1 and CCLR0 in TCR_8), and bit PB6DDR.
PAGE 653
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • PB5/A13/TIOCB7/TCLKG The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 7 settings (by bits MD3 to MD0 in TMDR_7, bits IOB3 to IOB0 in TIOR_7, and bits CCLR1 and CCLR0 in TCR_7), bits TPSC2 to TPSC0 in TCR_6, TCR_8, TCR_10, and TCR_11, and bit PB5DDR.
PAGE 654
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • PB4/A12/TIOCA7 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 7 settings (by bits MD3 to MD0 in TMDR_7, bits IOA3 to IOA0 in TIOR_7, and bits CCLR1 and CCLR0 in TCR_7), and bit PB4DDR.
PAGE 655
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • PB3/A11/TIOCD6/TCLKF The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 6 settings (by bits MD3 to MD0 in TMDR_6, bits IOD3 to IOD0 in TIORL_6, and bits CCLR2 to CCLR0 in TCR_6), bits TPSC2 to TPSC0 in TCR_6 to TCR_8, and bit PB3DDR.
PAGE 656
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • PB2/A10/TIOCC6/TCLKE The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 6 settings (by bits MD3 to MD0 in TMDR_6, bits IOC3 to IOC0 in TIORL_6, and bits CCLR2 to CCLR0 in TCR_6), bits TPSC2 to TPSC0 in TCR_6 to TCR_11, and bit PB2DDR.
PAGE 657
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • PB1/A9/TIOCB6 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 6 settings (by bits MD3 to MD0 in TMDR_6, bits IOB3 to IOB0 in TIORH_6, and bits CCLR2 to CCLR0 in TCR_6), and bit PB1DDR.
PAGE 658
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • PB0/A8/TIOCA6 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 6 settings (by bits MD3 to MD0 in TMDR_6, bits IOA3 to IOA0 in TIORH_6, and bits CCLR2 to CCLR0 in TCR_6), and bit PB0DDR.
PAGE 659
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.10.7 Port B Input Pull-Up MOS States Port B has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in modes 3, 4, and 7. The input pull-up MOS can be specified as on or off on a bit-by-bit basis. In modes 3, 4, and 7, when a PBDDR bit is cleared to 0, setting the corresponding PBPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.
PAGE 660
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.11 Port C Port C is an 8-bit I/O port that also has other functions. Port C has the following registers. • • • • • Port C data direction register (PCDDR) Port C data register (PCDR) Port C register (PORTC) Port C pull-up MOS control register (PCPCR) Port C open drain control register (PCODR) 10.11.1 Port C Data Direction Register (PCDDR) The individual bits of PCDDR specify input or output for the pins of port C.
PAGE 661
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.11.2 Port C Data Register (PCDR) PCDR stores output data for the port C pins. Bit Bit Name Initial Value R/W Description 7 PC7DR 0 R/W 6 PC6DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 5 PC5DR 0 R/W 4 PC4DR 0 R/W 3 PC3DR 0 R/W 2 PC2DR 0 R/W 1 PC1DR 0 R/W 0 PC0DR 0 R/W 10.11.3 Port C Register (PORTC) PORTC shows the pin states of port C.
PAGE 662
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.11.4 Port C Pull-Up MOS Control Register (PCPCR) PCPCR controls on/off of the input pull-up MOS for port C. PCPCR is valid in modes 4 and 7. Bit Bit Name Initial Value R/W Description 7 PC7PCR 0 R/W 6 PC6PCR 0 R/W When in a input port state, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin.
PAGE 663
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.11.6 Pin Functions Port C pins also function as the pins for TPU I/Os and address outputs. The correspondence between the register specification and the pin functions is shown below. • PC7/A7/TIOCB11 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 11 settings (by bits MD3 to MD0 in TMDR_11, bits IOB3 to IOB0 in TIOR_11, and bits CCLR1 and CCLR0 in TCR_11), and bit PC7DDR.
PAGE 664
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • PC6/A6/TIOCA11 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 11 settings (by bits MD3 to MD0 in TMDR_11, bits IOA3 to IOA0 in TIOR_11, and bits CCLR1 and CCLR0 in TCR_11), and bit PC6DDR.
PAGE 665
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • PC5/A5/TIOCB10 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 10 settings (by bits MD3 to MD0 in TMDR_10, bits IOB3 to IOB0 in TIOR_10, and bits CCLR1 and CCLR0 in TCR_10), and bit PC5DDR.
PAGE 666
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • PC4/A4/TIOCA10 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 10 settings (by bits MD3 to MD0 in TMDR_10, bits IOA3 to IOA0 in TIOR_10, and bits CCLR1 and CCLR0 in TCR_10), and bit PC4DDR.
PAGE 667
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • PC3/A3/TIOCD9 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 9 settings (by bits MD3 to MD0 in TMDR_9, bits IOD3 to IOD0 in TIORL_9, and bits CCLR2 to CCLR0 in TCR_9), and bit PC3DDR.
PAGE 668
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • PC2/A2/TIOCC9 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 9 settings (by bits MD3 to MD0 in TMDR_9, bits IOC3 to IOC0 in TIORL_9, and bits CCLR2 to CCLR0 in TCR_9), and bit PC2DDR.
PAGE 669
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • PC1/A1/TIOCB9 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 9 settings (by bits MD3 to MD0 in TMDR_9, bits IOB3 to IOB0 in TIORH_9, and bits CCLR2 to CCLR0 in TCR_9), and bit PC1DDR.
PAGE 670
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • PC0/A0/TIOCA9 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 9 settings (by bits MD3 to MD0 in TMDR_9, bits IOA3 to IOA0 in TIORH_9, and bits CCLR2 to CCLR0 in TCR_9), and bit PC0DDR.
PAGE 671
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.11.7 Port C Input Pull-Up MOS States Port C has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in modes 3, 4 and 7. The input pull-up MOS can be specified as on or off on a bit-by-bit basis. In modes 3, 4 and 7, when a PCDDR bit is cleared to 0, setting the corresponding PCPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.
PAGE 672
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.12 Port D Port D is an 8-bit I/O port that also has other functions. Port D has the following registers. • • • • • Port D data direction register (PDDDR) Port D data register (PDDR) Port D register (PORTD) Port D pull-up MOS control register (PDPCR) Port D open drain control register (PDODR) 10.12.1 Port D Data Direction Register (PDDDR) The individual bits of PDDDR specify input or output for the pins of port D.
PAGE 673
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.12.2 Port D Data Register (PDDR) PDDR stores output data for the port D pins. Bit Bit Name Initial Value R/W Description 7 PD7DR 0 R/W 6 PD6DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 5 PD5DR 0 R/W 4 PD4DR 0 R/W 3 PD3DR 0 R/W 2 PD2DR 0 R/W 1 PD1DR 0 R/W 0 PD0DR 0 R/W 10.12.3 Port D Register (PORTD) PORTD shows the pin states of port D.
PAGE 674
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.12.4 Port D Pull-Up MOS Control Register (PDPCR) PDPCR controls on/off of the input pull-up MOS for port D. PDPCR is valid in mode 7. Bit Bit Name Initial Value R/W Description 7 PD7PCR 0 R/W 6 PD6PCR 0 R/W When PDDDR = 0 (input port), setting the corresponding bit to 1 turns on the input pull-up MOS for that pin. 5 PD5PCR 0 R/W 4 PD4PCR 0 R/W 3 PD3PCR 0 R/W 2 PD2PCR 0 R/W 1 PD1PCR 0 R/W 0 PD0PCR 0 R/W 10.12.
PAGE 675
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.12.6 Pin Functions Port D pins also function as the pins for data I/Os and address outputs. The correspondence between the register specification and the pin functions is shown below.
PAGE 676
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.12.7 Port D Input Pull-Up MOS States Port D has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in modes 3 and 7. The input pull-up MOS can be specified as on or off on a bit-by-bit basis. In modes 3 and 7, when a PDDDR bit is cleared to 0, setting the corresponding PDPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.6 summarizes the input pull-up MOS states.
PAGE 677
H8S/2456, H8S/2456R, H8S/2454 Group 10.13 Section 10 I/O Ports Port E Port E is an 8-bit I/O port that also has other functions. Port E has the following registers. • • • • • Port E data direction register (PEDDR) Port E data register (PEDR) Port E register (PORTE) Port E pull-up MOS control register (PEPCR) Port E open drain control register (PEODR) 10.13.1 Port E Data Direction Register (PEDDR) The individual bits of PEDDR specify input or output for the pins of port E.
PAGE 678
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.13.2 Port E Data Register (PEDR) PEDR stores output data for the port E pins. Bit Bit Name Initial Value R/W Description 7 PE7DR 0 R/W 6 PE6DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 5 PE5DR 0 R/W 4 PE4DR 0 R/W 3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W 0 PE0DR 0 R/W 10.13.3 Port E Register (PORTE) PORTE shows the pin states of port E.
PAGE 679
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.13.4 Port E Pull-Up MOS Control Register (PEPCR) PEPCR controls on/off of the input pull-up MOS for port E. PEPCR is valid in 8-bit bus mode. Bit Bit Name Initial Value R/W 7 PE7PCR 0 R/W 6 PE6PCR 0 R/W 5 PE5PCR 0 R/W 4 PE4PCR 0 R/W 3 PE3PCR 0 R/W 2 PE2PCR 0 R/W 1 PE1PCR 0 R/W 0 PE0PCR 0 R/W Description When PEDDR = 0 (input port), setting the corresponding bit to 1 turns on the input pull-up MOS for that pin.
PAGE 680
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.13.6 Pin Functions Port E pins also function as the pins for data I/Os and address outputs. The correspondence between the register specification and the pin functions is shown below.
PAGE 681
H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.13.7 Port E Input Pull-Up MOS States Port E has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in 8-bit bus mode or in modes 3 and 7. The input pull-up MOS can be specified as on or off on a bit-by-bit basis. In 8-bit bus mode or in modes 3 and 7, when a PEDDR bit is cleared to 0, setting the corresponding PEPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.
PAGE 682
Section 10 I/O Ports 10.14 H8S/2456, H8S/2456R, H8S/2454 Group Port F Port F is an 8-bit I/O port that also has other functions. Port F has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.14.1 Port F Data Direction Register (PFDDR) The individual bits of PFDDR specify input or output for the pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports Bit Bit Name Initial Value R/W Description [H8S/2454 Group] Pins PF2 and PF1 function as CS output pins when the CS output enable bits (CS6E and CS5E) are set to 1, and as input ports when the bits are cleared to 0. When the CS output enable bits (CS6E and CS5E) are cleared to 0 and pins PF2 and PF1 are general I/O ports, the function can be switched with PFDDR.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.14.2 Port F Data Register (PFDR) PFDR stores output data for the port F pins. Bit Bit Name Initial Value R/W Description 7 PF7DR 0 R/W 6 PF6DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 5 PF5DR 0 R/W 4 PF4DR 0 R/W 3 PF3DR 0 R/W 2 PF2DR 0 R/W 1 PF1DR 0 R/W 0 PF0DR 0 R/W 10.14.3 Port F Register (PORTF) PORTF shows the pin states of port F.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.14.4 Port F Open Drain Control Register (PFODR) PFODR specifies the output type of each port F pin.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • PF6/AS/AH The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit MPXE in MPXCR of the bus controller, bit ASOE in PFCR2, and bit PF6DDR.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • PF3/LWR/SSO0-C The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of SSU, bit LWROE in PFCR2, bits SSOS1 and SSOS0 in PFCR5, and bit PF3DDR.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • PF2/LCAS/DQML*6/IRQ15-A/SSI0-C (H8S/2456 Group and H8S/2456R Group) The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of SSU, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bits ABW5 to ABW2 in ABWCR, bits SSI0S1 and SSI0S0 in PFCR5, and bit PF2DDR.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports SSU (1) (1) (3) (3) (2) (1) (2) (1) (1) (1) (1) (2) (1) (2) (2) (1) (2) settings SSUMS 0 0 1*1 BIDE 0 1*2 0 MSS 0 TE 1 0 1 0 0 1 0 1 1 0 0 1 0 1 1 0 1 RE 0 1 0 1 1 0 1 1 0 1 0 1 0 1 1 0 1 Pin state ⎯ ⎯ SSI SSI SSI ⎯ SSI ⎯ ⎯ ⎯ ⎯ SSI ⎯ SSI SSI ⎯ SSI input input output output input input input input [Legend] ⎯: Not used as the SSU pin (can be used as an I/O port).
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • Modes 3 and 7 (EXPE = 0) Areas 2 to 5 ⎯ CS6E ⎯ SSU settings (1) in table below PF2DDR 0 Pin function (2) in table below 1 PF2 input (3) in table below ⎯ 3 0* 1 PF2 output 4 SSI0-C output*2*4 SSI0-C input* * Notes: 1. When using as SSI0-C input, set SSI0S1 and SSI0S0 in PFCR5 to B'10 before other register setting. 2. When using as SSI0-C output, set SSI0S1 and SSI0S0 in PFCR5 to B'10 before other register setting. 3.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • PF1/UCAS/DQMU*6/IRQ14-A/SSCK0-C (H8S/2456 Group and H8S/2456R Group) The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and SCKS in SSCRH and bit SSUMS in SSCRL of SSU, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bits SSCK0S1 and SSCK0S0 in PFCR5, and bit PF1DDR.
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H8S/2456, H8S/2456R, H8S/2454 Group SSU settings (1) Section 10 I/O Ports (2) SSUMS (1) (3) (1) (2) 0 MSS (1) (3) 1 0 1 0 1 SCKS 0 1 0 1 0 1 0 1 Pin state ⎯ SSCK input ⎯ SSCK output ⎯ SSCK input ⎯ SSCK output [Legend] ⎯: Not used as the SSU pin (can be used as an I/O port). Note: See tables 20.4 to 20.6.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports SSU settings (1) (2) (1) SSUMS (3) (1) (2) (1) 0 MSS (3) 1 0 1 0 1 SCKS 0 1 0 1 0 1 0 1 Pin state ⎯ SSCK input ⎯ SSCK output ⎯ SSCK input ⎯ SSCK output [Legend] ⎯: Not used as the SSU pin (can be used as an I/O port). Note: See tables 20.4 to 20.6.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • Modes 3 and 7 (EXPE = 0) ⎯ WAITE SSU settings PF0DDR Pin function (1) in table below 0 (2) in table below (4) in table below 1 PF0 input 0* 5 0* PF0 output SCS0-C input* * 2 6 (3) in table below ⎯ 5 SCS0-C I/O* * SCS0-C output*3*6 4 6 ADTRG0-B input* 1 Notes: 1. ADTRG0-B input when the ADTRG0S bit in PFCR4 is 1, TRGS1 = TRGS0 = 0, and EXTRGS = 1 2.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • PF0/WAIT-A/ADTRG0-B/SCS0-C/OE-A (H8S/2454 Group) The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit WAITE in BCR of the bus controller, bit OEE in DRAMCR, bits MSS, CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of SSU, bits TRGS1, TRGS0, and EXTRGS in ADCR_0 of ADC, bit OES in PFCR2, bits ADTRG0S and WAITS in PFCR4, bits SCS0S1 and SCS0S0 in PFCR5, and bit PF0DDR.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • Modes 3 and 7 (EXPE = 0) OEE ⎯ Area 2 ⎯ WAITE ⎯ SSU settings (1) in table below PF0DDR 0 PF0 input Pin function (2) in table below (4) in table below (3) in table below 1 0*6 0*6 ⎯ PF0 output SCS0-C input*3*7 SCS0-C I/O*5*7 SCS0-C output*4*7 ADTRG0-B input* 2 Notes: 1. OE-A input when the OES bit in PFCR2 is 1. 2. ADTRG0-B input when TRGS1 = TRGS0 = 0, EXTRGS = 1, or TRGS1 = TRGS0 = EXTRGS = 1. 3.
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Section 10 I/O Ports 10.15 H8S/2456, H8S/2456R, H8S/2454 Group Port G Port G is a 7-bit I/O port that also has other functions. Port G has the following registers. • • • • • • Port G data direction register (PGDDR) Port G data register (PGDR) Port G register (PORTG) Port function control register 0 (PFCR0) Port function control register 4 (PFCR4) Port G open drain control register (PGODR) Page 668 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.15.1 Port G Data Direction Register (PGDDR) The individual bits of PGDDR specify input or output for the pins of port G. PGDDR cannot be read; if it is, an undefined value will be read.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.15.2 Port G Data Register (PGDR) PGDR stores output data for the port G pins. Bit Bit Name Initial Value R/W Description 7 ⎯ 0 ⎯ Reserved This bit is always read as 0, and cannot be modified. 6 PG6DR 0 R/W 5 PG5DR 0 R/W 4 PG4DR 0 R/W 3 PG3DR 0 R/W 2 PG2DR 0 R/W 1 PG1DR 0 R/W 0 PG0DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 10.15.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.15.4 Port G Open Drain Control Register (PGODR) PGODR specifies the output type of each port G pin. Bit Bit Name Initial Value R/W Description 7 ⎯ 0 ⎯ Reserved This bit is always read as 0. Only the initial value should be written to this bit.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • PG5/BACK-A The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit BRLE in BCR of the bus controller, bit BACKS in PFCR4, and bit PG5DDR.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • Modes 3 and 7 (EXPE = 0) BRLE ⎯ BREQOE BREQOS ⎯ CS4E 0 0 1 ⎯ PG4 input PG4 output CS4 output* PG4DDR Pin function Notes: * 1 Not supported in the H8S/2456 Group and H8S/2456R Group. • PG3/CS3/RAS3/CAS* The pin function is switched as shown below according to the combination of the operating mode, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS3E in PFCR0, and bit PG3DDR.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • PG2/CS2/ RAS2/RAS* The pin function is switched as shown below according to the combination of the operating mode, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS2E in PFCR0, and bit PG2DDR.
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H8S/2456, H8S/2456R, H8S/2454 Group 10.16 Section 10 I/O Ports Port H Note: Port H is not supported in the H8S/2454 Group. Port H is a 4-bit I/O port that also has other functions. Port H has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports Bit Bit Name Initial Value R/W 0 PH0DDR 0 W Description Pin PH1 functions as the SDRAMφ* output pin when the SDPSTP bit is 0 in the H8S/2456R Group. In the H8S/2456 Group or when the SDPSTP bit is 1 in the H8S/2456R Group, if bit CS5E is set to 1 while area 5 is specified as normal space, pin PH1 functions as the CS5 output pin when bit PH1DDR is set to 1, and functions as an I/O port when the bit is cleared to 0.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.16.2 Port H Data Register (PHDR) PHDR stores output data for the port H pins. Bit Bit Name Initial Value R/W Description 7 to 4 ⎯ All 0 ⎯ Reserved These bits are always read as 0 and cannot be modified. 3 PH3DR 0 R/W 2 PH2DR 0 R/W 1 PH1DR 0 R/W 0 PH0DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 10.16.3 Port H Register (PORTH) PORTH shows the pin states of port H.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.16.4 Port H Open Drain Control Register (PHODR) PHODR specifies the output type of each port H pin. Bit Bit Name 7 to 4 ⎯ Initial Value R/W Description All 0 ⎯ Reserved These bits are always read as 0. Only the initial values should be written to these bits.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.16.5 Pin Functions Port H pins also function as bus control signal I/Os and interrupt inputs. The correspondence between the register specification and the pin functions is shown below. • PH3/CS7/OE-A/CKE-A*2/IRQ7-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit OEE of the bus controller, bit OES in PFCR2, bit CS7E in PFCR0, and bit PH3DDR.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • PH2/CS6/IRQ6-B The pin function is switched as shown below according to the combination of the operating mode, bit CS6E in PFCR0, and bit PH2DDR.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports • PH0/CS4/RAS4/WE* The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS4E in PFCR0, and bit PH0DDR.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.17 Port J Note: Port J is not supported in the H8S/2454 Group and in the 145-pin package. Port J is a 3-bit I/O port. Port J has the following registers. • • • • Port J data direction register (PJDDR) Port J data register (PJDR) Port J register (PORT3) Port J open drain control register (PJODR) 10.17.1 Port J Data Direction Register (PJDDR) The individual bits of PJDDR specify input or output for the pins of port J.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.17.3 Port J Register (PORTJ) PORTJ shows the pin states of port J. PORTJ cannot be modified. Bit Bit Name Initial Value R/W Description 7 to 3 ⎯ Undefined ⎯ Reserved If these bits are read, they will return an undefined value. 2 PJ2 ⎯* R The pin state is always read from this register. 1 PJ1 ⎯* R 0 PJ0 ⎯* R If this register is read, the PJDR values are read for the bits with the corresponding PJDDR bits set to 1.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.17.5 Pin Functions Port J pins function only as I/O ports. The correspondence between the register specification and the pin functions is shown below. • PJ2 The PJ2 pin is an input-only pin. Pin function PJ2 input • PJ1, PJ0 The pin function is switched as shown below according to bit PJnDDR. PJnDDR Pin function 0 1 PJn input PJn output [Legend] n = 1 or 0 Page 684 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group 10.18 Section 10 I/O Ports Port Function Control Registers The port function controller performs I/O port control. The setting of input or output for each pin should be enabled only after the input or output destination has been selected. The port function controller has the following registers.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.18.2 Port Function Control Register 1 (PFCR1) PFCR1 enables or disables address output (A23 to A16). Bits 7 to 5 are valid in modes 1 and 2 and all the bits are valid in modes 4 and 7. Bit Bit Name Initial Value R/W Description 7 A23E 1 R/W Address 23 Enable Enables or disables output for address output 23 (A23).
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports Bit Bit Name Initial Value R/W Description 1 A17E 1 R/W Address 17 Enable Enables or disables output for address output 17 (A17). 0: DR output when PA1DDR = 1 1: A17 output when PA1DDR = 1 0 A16E 1 R/W Address 16 Enable Enables or disables output for address output 16 (A16). 0: DR output when PA0DDR = 1 1: A16 output when PA0DDR = 1 10.18.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports Bit Bit Name Initial Value R/W Description 1 OES 1 R/W OE Output Select Selects the OE/CKE* output pin port when the OEE bit in DRAMCR is set to 1 (enabling OE/CKE* output). 0: P35 is designated as OE-B/CKE-B*1 output pin. 1: [For H8S/2456 Group and H8S/2456R Group] PH3 is designated as OE-A/CKE-A* output pin. [For H8S/2454 Group] PH0 is designated as OE-A output pin. 0 ⎯ 0 ⎯ Reserved This bit is always read as 0.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports Bit Bit Name Initial Value R/W Description 4 TMRS 0 R/W TMR Pin Select Selects the output pins of TMO1 and TMO0 and input pins of TMCI1, TMCI0, TMRI1, and TMRI0. 0: [For H8S/2456 Group and H8S/2456R Group] P65/TMO1-A, P64/TMO0-A, P63/TMCI1-A, P62/TMCI0-A, P61/TMRI1-A, and P60/TMRI0-A are selected. [For H8S/2454 Group] P25/TMO1-A and P20/TMRI0-A are selected.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.18.5 Port Function Control Register 4 (PFCR4) PFCR4 switches the functions of the WAIT input pin, BREQ input pin, BACK output pin, BREQO output pin, TxD4 output pin, RxD4 input pin, and SCK4 input/output pin. Bit Bit Name Initial Value R/W Description 7 WAITS 0 R/W WAIT Pin Select Selects the WAIT input pin. 0: PF0/WAIT-A is selected 1: P25/WAIT-B is selected 6 BREQS 0 R/W BREQ Pin Select Selects the BREQ input pin.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports Bit Bit Name Initial Value R/W Description 1 RXD4S 0 R/W Enables RxD4-B input. Enables or disables RxD4-B input. 0: PA2 is designated as I/O port. 1: PA2 is designated as RxD4-B output pin. 0 SCK4S 0 R/W SCK4 Pin Select Selects the SCK4 input/output pin. 0: P34/SCK4-A is selected 1: PA3/SCK4-B is selected R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 10 I/O Ports 10.18.6 Port Function Control Register 5 (PFCR5) PFCR5 switches the functions of the SSU input/output pins. Bit Bit Name Initial Value R/W Description 7 SSO0S1 0 R/W SSO0 Pin Select 6 SSO0S0 0 R/W Selects the SSO0 input/output pin. 00: P14/SSO0-A is selected 01: PA7/SSO0-B is selected 10: PF3/SSO0-C is selected 11: Setting prohibited 5 SSI0S1 0 R/W SSI0 Pin Select 4 SSI0S0 0 R/W Selects the SSI0 input/output pin.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Section 11 16-Bit Timer Pulse Unit (TPU) This LSI has two on-chip 16-bit timer pulse units (TPU: unit 0 and unit 1) which each comprises six 16-bit timer channels, resulting in a total of 12 channels. The functions of unit 0 are listed in table 11.1, and the functions of unit 1 are listed in table 11.2. The block diagram of unit 0 is shown in figure 11.1 and the block diagram of unit 1 is shown in figure 11.2.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
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H8S/2456, H8S/2456R, H8S/2454 Group Item Channel 0 Section 11 16-Bit Timer Pulse Unit (TPU) Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 DTC TGR activation compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture DMAC TGRA_0 activation compare match or input capture TGRA_1 compare match or input capture TGRA_2 compare match or input captur
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
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H8S/2456, H8S/2456R, H8S/2454 Group Item Channel 6 Section 11 16-Bit Timer Pulse Unit (TPU) Channel 7 Channel 8 Channel 9 Channel 10 Channel 11 DTC TGR activation compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture DMAC ⎯ activation ⎯ ⎯ ⎯ ⎯ ⎯ A/D TGRA_6 converter compare trigger match or input capture TGRA_7 compare match or input cap
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H8S/2456, H8S/2456R, H8S/2454 Group TGRD TGRB TGRC TGRB Interrupt request signals Channel 3: TGI3A TGI3B TGI3C TGI3D TCI3V Channel 4: TGI4A TGI4B TCI4V TCI4U Channel 5: TGI5A TGI5B TCI5V TCI5U Internal data bus A/D conversion start request signal TGRD TGRB TGRB TGRB PPG output trigger signal TGRC TCNT TCNT TGRA TCNT TGRA Bus interface TGRB TCNT TCNT TGRA TCNT TGRA Module data bus TGRA TSR TSR TIER TSR TIER TIOR TIORH TIORL TIER: TSR: TGR (A, B, C, D): TCNT: TGRA TSR TIER TSR TS
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H8S/2456, H8S/2456R, H8S/2454 Group TIER: TSR: TGR (A, B, C, D): TCNT: TGRD TGRB TGRC TGRB Interrupt request signals Channel 9: TGI9A TGI9B TGI9C TGI9D TCI9V Channel 10: TGI10A TGI10B TCI10V TCI10U Channel 11: TGI11A TGI11B TCI11V TCI11U Internal data bus TGRD TGRB TGRB TGRB A/D conversion start request signal TGRC TCNT TCNT TGRA TCNT TGRA TGRA Bus interface TGRB TCNT TCNT TGRA TCNT Module data bus TGRA TGRA TSR TIER TSR TIER TSR TIER TSTR TSYR TSR TIER TSR TIER TIOR TIORH TIORL
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.2 Input/Output Pins Table 11.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Unit Channel Symbol I/O Function 0 4 TIOCA4 I/O TGRA_4 input capture input/output compare output/ PWM output pin TIOCB4 I/O TGRB_4 input capture input/output compare output/ PWM output pin TIOCA5 I/O TGRA_5 input capture input/output compare output/ PWM output pin TIOCB5 I/O TGRB_5 input capture input/output compare output/ PWM output pin TCLKE Input External clock E input pin (Channel 7 and 11 phase counting
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Unit Channel Symbol I/O Function 1* 9 TIOCA9 I/O TGRA_9 input capture input/output compare output/ PWM output pin TIOCB9 I/O TGRB_9 input capture input/output compare output/ PWM output pin TIOCC9 I/O TGRC_9 input capture input/output compare output/ PWM output pin TIOCD9 I/O TGRD_9 input capture input/output compare output/ PWM output pin TIOCA10 I/O TGRA_10 input capture input/output compare output/PWM outp
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H8S/2456, H8S/2456R, H8S/2454 Group 11.3 Section 11 16-Bit Timer Pulse Unit (TPU) Register Descriptions The TPU has the following registers in each channel. The descriptions in this section refer to the registers of unit 0.
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Section 11 16-Bit Timer Pulse Unit (TPU) H8S/2456, H8S/2456R, H8S/2454 Group Channel 2 • Timer control register_2 (TCR_2) • Timer mode register_2 (TMDR_2) • Timer I/O control register_2 (TIOR_2) • Timer interrupt enable register_2 (TIER_2) • Timer status register_2 (TSR_2) • Timer counter_2 (TCNT_2) • Timer general register A_2 (TGRA_2) • Timer general register B_2 (TGRB_2) Channel 3 • Timer control register_3 (TCR_3) • Timer mode register_3 (TMDR_3) • Timer I/O control register H_3 (TIORH_3) • Timer I/O
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Channel 5 • Timer control register_5 (TCR_5) • Timer mode register_5 (TMDR_5) • Timer I/O control register_5 (TIOR_5) • Timer interrupt enable register_5 (TIER_5) • Timer status register_5 (TSR_5) • Timer counter_5 (TCNT_5) • Timer general register A_5 (TGRA_5) • Timer general register B_5 (TGRB_5) Common Registers of Unit 0 • Timer start register (TSTR) • Timer synchronous register (TSYR) Unit 1: Channel 6 • Timer control regist
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Section 11 16-Bit Timer Pulse Unit (TPU) H8S/2456, H8S/2456R, H8S/2454 Group Channel 7 • Timer control register_7 (TCR_7) • Timer mode register_7 (TMDR_7) • Timer I/O control register_7 (TIOR_7) • Timer interrupt enable register_7 (TIER_7) • Timer status register_7 (TSR_7) • Timer counter_7 (TCNT_7) • Timer general register A_7 (TGRA_7) • Timer general register B_7 (TGRB_7) Channel 8 • Timer control register_8 (TCR_8) • Timer mode register_8 (TMDR_8) • Timer I/O control register_8 (TIOR_8) • Timer interru
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Channel 10 • Timer control register_10 (TCR_10) • Timer mode register_10 (TMDR_10) • Timer I/O control register_10 (TIOR_10) • Timer interrupt enable register_10 (TIER_10) • Timer status register_10 (TSR_10) • Timer counter_10 (TCNT_10) • Timer general register A_10 (TGRA_10) • Timer general register B_10 (TGRB_10) Channel 11 • Timer control register_11 (TCR_11) • Timer mode register_11 (TMDR_11) • Timer I/O control register_11 (
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.1 Timer Control Register (TCR) The TCR registers control the TCNT operation for each channel. The TPU has a total of six TCR registers, one for each channel. TCR register settings should be made only when TCNT operation is stopped. Bit Bit Name Initial Value R/W Description 7 CCLR2 0 R/W Counter Clear 2 to 0 6 CCLR1 0 R/W 5 CCLR0 0 R/W These bits select the TCNT counter clearing source. See tables 11.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
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H8S/2456, H8S/2456R, H8S/2454 Group 11.3.2 Section 11 16-Bit Timer Pulse Unit (TPU) Timer Mode Register (TMDR) TMDR registers are used to set the operating mode for each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings should be made only when TCNT operation is stopped. Bit Bit Name Initial Value R/W Description 7 ⎯ 1 ⎯ Reserved 6 ⎯ 1 ⎯ These bits are always read as 1 and cannot be modified.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.12 MD3 to MD0 Bit 3 1 MD3* Bit 2 MD2*2 Bit 1 MD1 Bit 0 MD0 Description 0 0 0 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 1 1 0 1 1 x x 0 Phase counting mode 3 1 Phase counting mode 4 x ⎯ [Legend] x: Don't care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2.
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H8S/2456, H8S/2456R, H8S/2454 Group 11.3.3 Section 11 16-Bit Timer Pulse Unit (TPU) Timer I/O Control Register (TIOR) TIOR registers control the TGR registers. The TPU has eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0).
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 748
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 750
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 754
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 755
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 756
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 757
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 762
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.4 Timer Interrupt Enable Register (TIER) TIER registers control enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. Bit Bit Name Initial value R/W Description 7 TTGE 0 R/W A/D Conversion Start Request Enable Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Bit Bit Name Initial value R/W Description 2 TGIEC 0 R/W TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.5 Timer Status Register (TSR) TSR registers indicate the status of each channel. The TPU has six TSR registers, one for each channel. Bit Bit Name Initial value R/W Description 7 TCFD 1 R Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified.
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H8S/2456, H8S/2456R, H8S/2454 Group Bit 3 Bit Name TGFD Section 11 16-Bit Timer Pulse Unit (TPU) Initial value R/W Description 0 R/(W)* 1 Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Bit 1 Bit Name TGFB Initial value R/W Description 0 R/(W)* 1 Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match.
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H8S/2456, H8S/2456R, H8S/2454 Group 11.3.6 Section 11 16-Bit Timer Pulse Unit (TPU) Timer Counter (TCNT) The TCNT registers are 16-bit readable/writable counters. The TPU has six TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset, or in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 11.3.
PAGE 768
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.9 Timer Synchronous Register (TSYR) TSYR selects independent operation or synchronous operation for the TCNT counters of channels 0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit Bit Name Initial value R/W Description 7 ⎯ 0 ⎯ Reserved 6 ⎯ 0 ⎯ The write value should always be 0.
PAGE 769
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.10 Timer Start Register B (TSTRB) TSTRB selects operation/stoppage for channels 6 to 11. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bit Bit Name Initial value R/W Description 7 ⎯ 0 ⎯ Reserved 6 ⎯ 0 ⎯ The write value should always be 0. 5 CST11 0 R/W Counter Start 11 to 6 4 CST10 0 R/W These bits select operation or stoppage for TCNT.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.11 Timer Synchronous Register B (TSYRB) TSYRB selects independent operation or synchronous operation for the TCNT counters of channels 6 to 11. A channel performs synchronous operation when the corresponding bit in TSYRB is set to 1. Bit Bit Name Initial value R/W Description 7 ⎯ 0 ⎯ Reserved 6 ⎯ 0 ⎯ The write value should always be 0.
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H8S/2456, H8S/2456R, H8S/2454 Group 11.4 Operation 11.4.1 Basic Functions Section 11 16-Bit Timer Pulse Unit (TPU) Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR can be used as an input capture register or output compare register. (1) Counter Operation When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR.
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H8S/2456, H8S/2456R, H8S/2454 Group (b) Section 11 16-Bit Timer Pulse Unit (TPU) Free-running count operation and periodic count operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (changes from H'FFFF to H'0000), the TCFV bit in TSR is set to 1.
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Section 11 16-Bit Timer Pulse Unit (TPU) H8S/2456, H8S/2456R, H8S/2454 Group When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR.
PAGE 775
H8S/2456, H8S/2456R, H8S/2454 Group (2) Section 11 16-Bit Timer Pulse Unit (TPU) Waveform Output by Compare Match The TPU can perform 0, 1, or toggle output from the corresponding output pin using a compare match. (a) Example of setting procedure for waveform output by compare match Figure 11.6 shows an example of the setting procedure for waveform output by a compare match.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) (b) Examples of waveform output operation Figure 11.7 shows an example of 0 output/1 output. In this example, TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level match, the pin level does not change.
PAGE 777
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Figure 11.8 shows an example of toggle output. In this example TCNT has been designated as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA Time H'0000 Toggle output TIOCB Toggle output TIOCA Figure 11.
PAGE 778
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) (3) Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detection edge. For channels 0, 1, 3, 4, 6, 7, 9, and 10 it is also possible to specify another channel’s counter input clock or compare match signal as the input capture source.
PAGE 779
H8S/2456, H8S/2456R, H8S/2454 Group (b) Section 11 16-Bit Timer Pulse Unit (TPU) Example of input capture operation Figure 11.10 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
PAGE 780
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) (1) Example of Synchronous Operation Setting Procedure Figure 11.11 shows an example of the synchronous operation setting procedure.
PAGE 781
H8S/2456, H8S/2456R, H8S/2454 Group (2) Section 11 16-Bit Timer Pulse Unit (TPU) Example of Synchronous Operation Figure 11.12 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOCA0, TIOCA1, and TIOCA2.
PAGE 782
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.4.3 Buffer Operation Buffer operation, provided for channels 0, 3, 6, and 9, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or a compare match register. Table 11.29 shows the register combinations used in buffer operation. Table 11.
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H8S/2456, H8S/2456R, H8S/2454 Group • Section 11 16-Bit Timer Pulse Unit (TPU) When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 11.14. Input capture signal Timer general register Buffer register TCNT Figure 11.14 Input Capture Buffer Operation (1) Example of Buffer Operation Setting Procedure Figure 11.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) (2) Examples of Buffer Operation (a) When TGR is an output compare register Figure 11.16 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B.
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H8S/2456, H8S/2456R, H8S/2454 Group (b) Section 11 16-Bit Timer Pulse Unit (TPU) When TGR is an input capture register Figure 11.17 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge.
PAGE 786
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4, channel 7, or channel 10) counter clock at overflow/underflow of TCNT_2 (TCNT_5, TCNT_8, or TCNT_11) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 11.
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H8S/2456, H8S/2456R, H8S/2454 Group (2) Section 11 16-Bit Timer Pulse Unit (TPU) Examples of Cascaded Operation Figure 11.19 illustrates the operation when counting upon TCNT_2 overflow/underflow has been set for TCNT_1, TGRA_1 and TGRA_2 have been designated as input capture registers, and the TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2.
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Section 11 16-Bit Timer Pulse Unit (TPU) 11.4.5 H8S/2456, H8S/2456R, H8S/2454 Group PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Settings of TGR registers can output a PWM waveform in the range of 0–% to 100–% duty cycle. Designating TGR compare match as the counter clearing source enables the cycle to be set in that register.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 790
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) (1) Example of PWM Mode Setting Procedure Figure 11.21 shows an example of the PWM mode setting procedure. PWM mode Select counter clock [1] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source.
PAGE 791
H8S/2456, H8S/2456R, H8S/2454 Group (2) Section 11 16-Bit Timer Pulse Unit (TPU) Examples of PWM Mode Operation Figure 11.22 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the cycle, and the values set in TGRB registers as the duty cycle.
PAGE 792
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Figure 11.23 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), to output a 5-phase PWM waveform.
PAGE 793
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Figure 11.24 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode.
PAGE 794
Section 11 16-Bit Timer Pulse Unit (TPU) 11.4.6 H8S/2456, H8S/2456R, H8S/2454 Group Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, 5, 7, 8, 10, and 11.
PAGE 795
H8S/2456, H8S/2456R, H8S/2454 Group (1) Section 11 16-Bit Timer Pulse Unit (TPU) Example of Phase Counting Mode Setting Procedure Figure 11.25 shows an example of the phase counting mode setting procedure. [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. Phase counting mode Select phase counting mode [1] Start count [2] Figure 11.
PAGE 796
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 797
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) b. Phase counting mode 2 Figure 11.27 shows an example of phase counting mode 2 operation, and table 11.34 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 11.27 Example of Phase Counting Mode 2 Operation Table 11.
PAGE 798
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) c. Phase counting mode 3 Figure 11.28 shows an example of phase counting mode 3 operation, and table 11.35 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count Time Figure 11.28 Example of Phase Counting Mode 3 Operation Table 11.
PAGE 799
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) d. Phase counting mode 4 Figure 11.29 shows an example of phase counting mode 4 operation, and table 11.36 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count Time Figure 11.29 Example of Phase Counting Mode 4 Operation Table 11.
PAGE 800
Section 11 16-Bit Timer Pulse Unit (TPU) (3) H8S/2456, H8S/2456R, H8S/2454 Group Phase Counting Mode Application Example Figure 11.30 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB.
PAGE 801
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Channel 1 TCLKA TCLKB Edge detection circuit TCNT_1 TGRA_1 (speed cycle capture) TGRB_1 (position cycle capture) TCNT_0 TGRA_0 (speed control cycle) + - TGRC_0 (position control cycle) + - TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 Figure 11.30 Phase Counting Mode Application Example R01UH0309EJ0500 Rev. 5.
PAGE 802
Section 11 16-Bit Timer Pulse Unit (TPU) 11.5 H8S/2456, H8S/2456R, H8S/2454 Group Interrupt Sources There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1.
PAGE 803
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 804
Section 11 16-Bit Timer Pulse Unit (TPU) H8S/2456, H8S/2456R, H8S/2454 Group Unit Channel Name Interrupt Source Interrupt Flag DTC Activation DMAC Activation 1 TGI6A TGRA_6 input capture/compare match TGFA_6 Possible Not possible TGI6B TGRB_6 input capture/compare match TGFB_6 Possible Not possible TGI6C TGRC_6 input capture/compare match TGFC_6 Possible Not possible TGI6D TGRD_6 input capture/compare match TGFD_6 Possible Not possible 6 7 8 9 10 11 Note: TCI6V TCNT_6 ov
PAGE 805
H8S/2456, H8S/2456R, H8S/2454 Group (1) Section 11 16-Bit Timer Pulse Unit (TPU) Input Capture/Compare Match Interrupt An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0.
PAGE 806
Section 11 16-Bit Timer Pulse Unit (TPU) 11.6 H8S/2456, H8S/2456R, H8S/2454 Group DTC Activation The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 9, Data Transfer Controller (DTC). A total of 32 TPU input capture/compare match interrupts can be used as DTC activation sources, four each for channels 0, 3, 6, and 9, and two each for channels 1, 2, 4, 5, 7, 8, 10, and 11. 11.
PAGE 807
H8S/2456, H8S/2456R, H8S/2454 Group 11.9 Operation Timing 11.9.1 Input/Output Timing (1) Section 11 16-Bit Timer Pulse Unit (TPU) TCNT Count Timing Figure 11.31 shows TCNT count timing in internal clock operation, and figure 11.32 shows TCNT count timing in external clock operation. φ Internal clock Falling edge Rising edge TCNT input clock N–1 TCNT N N+1 N+2 Figure 11.
PAGE 808
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) (2) Output Compare Output Timing A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin. After a match between TCNT and TGR, the compare match signal is not generated until the (TIOC pin) TCNT input clock is generated.
PAGE 809
H8S/2456, H8S/2456R, H8S/2454 Group (3) Section 11 16-Bit Timer Pulse Unit (TPU) Input Capture Signal Timing Figure 11.34 shows input capture signal timing. φ Input capture input Input capture signal N+1 N TCNT N+2 N TGR N+2 Figure 11.34 Input Capture Input Signal Timing (4) Timing for Counter Clearing by Compare Match/Input Capture Figure 11.35 shows the timing when counter clearing by compare match occurrence is specified, and figure 11.
PAGE 810
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) φ Input capture signal Counter clear signal TCNT TGR N H'0000 N Figure 11.36 Counter Clear Timing (Input Capture) Page 780 of 1408 R01UH0309EJ0500 Rev. 5.
PAGE 811
H8S/2456, H8S/2456R, H8S/2454 Group (5) Section 11 16-Bit Timer Pulse Unit (TPU) Buffer Operation Timing Figures 11.37 and 11.38 show the timings in buffer operation. φ TCNT n n+1 Compare match signal TGRA, TGRB n TGRC, TGRD N N Figure 11.37 Buffer Operation Timing (Compare Match) φ Input capture signal TCNT N TGRA, TGRB n TGRC, TGRD N+1 N N+1 n N Figure 11.38 Buffer Operation Timing (Input Capture) R01UH0309EJ0500 Rev. 5.
PAGE 812
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.9.2 (1) Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match Figure 11.39 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and the TGI interrupt request signal timing. φ TCNT input clock TCNT N TGR N N+1 Compare match signal TGF flag TGI interrupt Figure 11.39 TGI Interrupt Timing (Compare Match) Page 782 of 1408 R01UH0309EJ0500 Rev. 5.
PAGE 813
H8S/2456, H8S/2456R, H8S/2454 Group (2) Section 11 16-Bit Timer Pulse Unit (TPU) TGF Flag Setting Timing in Case of Input Capture Figure 11.40 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and the TGI interrupt request signal timing. φ Input capture signal N TCNT TGR N TGF flag TGI interrupt Figure 11.40 TGI Interrupt Timing (Input Capture) R01UH0309EJ0500 Rev. 5.
PAGE 814
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) (3) TCFV Flag/TCFU Flag Setting Timing Figure 11.41 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and the TCIV interrupt request signal timing. Figure 11.42 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and the TCIU interrupt request signal timing. φ TCNT input clock TCNT (overflow) H'FFFF H'0000 Overflow signal TCFV flag TCIV interrupt Figure 11.
PAGE 815
H8S/2456, H8S/2456R, H8S/2454 Group (4) Section 11 16-Bit Timer Pulse Unit (TPU) Status Flag Clearing Timing After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 11.43 shows the timing for status flag clearing by the CPU, and figure 11.44 shows the timing for status flag clearing by the DTC or DMAC.
PAGE 816
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.10 Usage Notes 11.10.1 Module Stop Function Setting TPU operation can be disabled or enabled using the module stop control register. The initial setting is for TPU operation to be halted. Register access is enabled by clearing the module stop state. For details, refer to section 24, Power-Down Modes. 11.10.2 Input Clock Restrictions The input clock pulse width must be at least 1.
PAGE 817
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.3 Caution on Cycle Setting When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: φ f= (N + 1) Where f: Counter frequency φ: Operating frequency N: TGR set value 11.10.
PAGE 818
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.5 Contention between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 11.47 shows the timing in this case. TCNT write cycle T2 T1 φ TCNT address Address Write signal TCNT input clock TCNT N M TCNT write data Figure 11.
PAGE 819
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.6 Contention between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is disabled. A compare match also does not occur when the same value as before is written. Figure 11.48 shows the timing in this case.
PAGE 820
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.7 Contention between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 11.49 shows the timing in this case. TGR write cycle T2 T1 φ Buffer register address Address Write signal Compare match signal Buffer register write data Buffer register TGR N M N Figure 11.
PAGE 821
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.8 Contention between TGR Read and Input Capture If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 11.50 shows the timing in this case. TGR read cycle T1 T2 φ TGR address Address Read signal Input capture signal TGR X Internal data bus M M Figure 11.
PAGE 822
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.9 Contention between TGR Write and Input Capture If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 11.51 shows the timing in this case. TGR write cycle T2 T1 φ Address TGR address Write signal Input capture signal TCNT TGR M M Figure 11.
PAGE 823
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.10 Contention between Buffer Register Write and Input Capture If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 11.52 shows the timing in this case.
PAGE 824
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.11 Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 11.53 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR. φ TCNT input clock TCNT H'FFFF H'0000 Counter clearing signal TGF Disabled TCFV Figure 11.
PAGE 825
H8S/2456, H8S/2456R, H8S/2454 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.12 Contention between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, when overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 11.54 shows the operation timing when there is contention between TCNT write and overflow.
PAGE 826
Section 11 16-Bit Timer Pulse Unit (TPU) Page 796 of 1408 H8S/2456, H8S/2456R, H8S/2454 Group R01UH0309EJ0500 Rev. 5.
PAGE 827
H8S/2456, H8S/2456R, H8S/2454 Group Section 12 Programmable Pulse Generator (PPG) Section 12 Programmable Pulse Generator (PPG) The programmable pulse generator (PPG) provides pulse outputs by using the 16-bit timer pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (groups 3 to 0) that can operate both simultaneously and independently. The block diagram of PPG is shown in figure 12.1. 12.
PAGE 828
H8S/2456, H8S/2456R, H8S/2454 Group Section 12 Programmable Pulse Generator (PPG) Compare match signals Control logic PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 PO7 PO6 PO5 PO4 PO3 PO2 PO1 PO0 [Legend] PMR: PCR: NDERH: NDERL: NDRH: NDRL: PODRH: PODRL: NDERH NDERL PMR PCR Pulse output pins, group 3 PODRH NDRH (NDRHH, NDRHL) PODRL NDRL (NDRLH, NDRLL) Pulse output pins, group 2 Internal data bus Pulse output pins, group 1 Pulse output pins, group 0 PPG output mode register PPG output control regist
PAGE 829
H8S/2456, H8S/2456R, H8S/2454 Group 12.2 Section 12 Programmable Pulse Generator (PPG) Input/Output Pins Table 12.1 shows the PPG pin configuration. Table 12.1 Pin Configuration Pin Name I/O Function PO15 Output Group 3 pulse output PO14 Output PO13 Output PO12 Output PO11 Output PO10 Output PO9 Output PO8 Output PO7 Output PO6 Output PO5 Output PO4 Output PO3 Output PO2 Output PO1 Output PO0 Output R01UH0309EJ0500 Rev. 5.
PAGE 830
Section 12 Programmable Pulse Generator (PPG) 12.3 H8S/2456, H8S/2456R, H8S/2454 Group Register Descriptions The PPG has the following registers. • • • • • • • • Next data enable register H (NDERH) Next data enable register L (NDERL) Output data register H (PODRH) Output data register L (PODRL) Next data register H (NDRH) Next data register L (NDRL) PPG output control register (PCR) PPG output mode register (PMR) Page 800 of 1408 R01UH0309EJ0500 Rev. 5.
PAGE 831
H8S/2456, H8S/2456R, H8S/2454 Group 12.3.1 Section 12 Programmable Pulse Generator (PPG) Next Data Enable Registers H and L (NDERH, NDERL) NDERH and NDERL enable or disable pulse output on a bit-by-bit basis. For outputting pulse by the PPG, set the corresponding DDR to 1.
PAGE 832
H8S/2456, H8S/2456R, H8S/2454 Group Section 12 Programmable Pulse Generator (PPG) 12.3.2 Output Data Registers H and L (PODRH, PODRL) PODRH and PODRL store output data for use in pulse output. A bit that has been set for pulse output by NDER is read-only and cannot be modified.
PAGE 833
H8S/2456, H8S/2456R, H8S/2454 Group 12.3.3 Section 12 Programmable Pulse Generator (PPG) Next Data Registers H and L (NDRH, NDRL) NDRH and NDRL store the next data for pulse output. The NDR addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. • NDRH (NDRHH, NDRHL)* If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below.
PAGE 834
H8S/2456, H8S/2456R, H8S/2454 Group Section 12 Programmable Pulse Generator (PPG) • NDRHL* Bit Bit Name Initial Value R/W Description 7 to 4 ⎯ All 1 ⎯ Reserved 1 is always read and write is disabled. 3 NDR11 0 R/W Next Data Register 11 to 8 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR.
PAGE 835
H8S/2456, H8S/2456R, H8S/2454 Group • Section 12 Programmable Pulse Generator (PPG) NDRLH* Bit Bit Name Initial Value R/W Description 7 NDR7 0 R/W Next Data Register 7 to 4 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. 3 to 0 ⎯ All 1 ⎯ Reserved 1 is always read and write is disabled.
PAGE 836
H8S/2456, H8S/2456R, H8S/2454 Group Section 12 Programmable Pulse Generator (PPG) 12.3.4 PPG Output Control Register (PCR) PCR selects output trigger signals on a group-by-group basis. For details on output trigger selection, refer to section 12.3.5, PPG Output Mode Register (PMR). Bit Bit Name Initial Value R/W Description 7 G3CMS1 1 R/W Group 3 Compare Match Select 1 and 0 6 G3CMS0 1 R/W Select output trigger of pulse output group 3.
PAGE 837
H8S/2456, H8S/2456R, H8S/2454 Group 12.3.5 Section 12 Programmable Pulse Generator (PPG) PPG Output Mode Register (PMR) PMR selects the pulse output mode of the PPG for each group. If inverted output is selected, a low-level pulse is output when PODRH is 1 and a high-level pulse is output when PODRH is 0. If non-overlapping operation is selected, PPG updates its output values at compare match A or B of the TPU that becomes the output trigger. For details, refer to section 12.4.
PAGE 838
H8S/2456, H8S/2456R, H8S/2454 Group Section 12 Programmable Pulse Generator (PPG) Bit Bit Name Initial Value R/W Description 3 G3NOV 0 R/W Group 3 Non-Overlap Selects normal or non-overlapping operation for pulse output group 3.
PAGE 839
H8S/2456, H8S/2456R, H8S/2454 Group 12.4 Section 12 Programmable Pulse Generator (PPG) Operation Figure 12.2 shows an overview diagram of the PPG. PPG pulse output is enabled when the corresponding bits in P1DDR, P2DDR, and NDER are set to 1. An initial output value is determined by its corresponding PODR initial setting. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values.
PAGE 840
H8S/2456, H8S/2456R, H8S/2454 Group Section 12 Programmable Pulse Generator (PPG) 12.4.1 Output Timing If pulse output is enabled, NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 12.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. φ N TCNT TGRA N+1 N Compare match A signal n NDRH PODRH PO8 to PO15 m n m n Figure 12.
PAGE 841
H8S/2456, H8S/2456R, H8S/2454 Group 12.4.2 Section 12 Programmable Pulse Generator (PPG) Sample Setup Procedure for Normal Pulse Output Figure 12.4 shows a sample procedure for setting up normal pulse output. Normal PPG output Select TGR functions [1] Set TGRA value [2] Set counting operation [3] Select interrupt request [4] Set initial output data [5] Enable pulse output [6] Select output trigger [7] [1] Set TIOR to make TGRA an output compare register (with output disabled).
PAGE 842
H8S/2456, H8S/2456R, H8S/2454 Group Section 12 Programmable Pulse Generator (PPG) 12.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output) Figure 12.5 shows an example in which pulse output is used for cyclic five-phase pulse output. TCNT value Compare match TCNT TGRA H'0000 Time 80 NDRH PODRH 00 C0 80 40 C0 60 40 20 60 30 20 10 30 18 10 08 18 88 08 80 88 C0 80 40 C0 PO15 PO14 PO13 PO12 PO11 Figure 12.
PAGE 843
H8S/2456, H8S/2456R, H8S/2454 Group 12.4.4 Section 12 Programmable Pulse Generator (PPG) Non-Overlapping Pulse Output During non-overlapping operation, transfer from NDR to PODR is performed as follows: • • NDR bits are always transferred to PODR bits at compare match A. At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred if their value is 1. Figure 12.6 illustrates the non-overlapping pulse output operation.
PAGE 844
H8S/2456, H8S/2456R, H8S/2454 Group Section 12 Programmable Pulse Generator (PPG) Compare match A Compare match B Write to NDR Write to NDR NDR PODR 0 output 0/1 output Write to NDR Do not write here to NDR here 0 output 0/1 output Do not write to NDR here Write to NDR here Figure 12.7 Non-Overlapping Operation and NDR Write Timing Page 814 of 1408 R01UH0309EJ0500 Rev. 5.
PAGE 845
H8S/2456, H8S/2456R, H8S/2454 Group 12.4.5 Section 12 Programmable Pulse Generator (PPG) Sample Setup Procedure for Non-Overlapping Pulse Output Figure 12.8 shows a sample procedure for setting up non-overlapping pulse output.
PAGE 846
H8S/2456, H8S/2456R, H8S/2454 Group Section 12 Programmable Pulse Generator (PPG) 12.4.6 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output) Figure 12.9 shows an example in which pulse output is used for four-phase complementary nonoverlapping pulse output. TCNT value TGRB TCNT TGRA H'0000 NDRH PODRH Time 65 95 00 95 59 05 65 56 41 59 95 50 56 65 14 95 05 65 Non-overlap margin PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 12.
PAGE 847
H8S/2456, H8S/2456R, H8S/2454 Group Section 12 Programmable Pulse Generator (PPG) 1. Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers. Set the trigger period in TGRB and the non-overlap margin in TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt. 2.
PAGE 848
H8S/2456, H8S/2456R, H8S/2454 Group Section 12 Programmable Pulse Generator (PPG) 12.4.7 Inverted Pulse Output If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 12.10 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the settings of figure 12.9.
PAGE 849
H8S/2456, H8S/2456R, H8S/2454 Group 12.4.8 Section 12 Programmable Pulse Generator (PPG) Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal. Figure 12.11 shows the timing of this output. φ TIOC pin Input capture signal NDR N PODR M PO M N N Figure 12.
PAGE 850
Section 12 Programmable Pulse Generator (PPG) 12.5 Usage Notes 12.5.1 Module Stop Function Setting H8S/2456, H8S/2456R, H8S/2454 Group PPG operation can be disabled or enabled using the module stop control register. The initial value is for PPG operation to be halted. Register access is enabled by clearing the module stop state. For details, refer to section 24, Power-Down Modes. 12.5.2 Operation of Pulse Output Pins Pins PO0 to PO15 are also used for other peripheral functions such as the TPU.
PAGE 851
H8S/2456, H8S/2456R, H8S/2454 Group Section 13 8-Bit Timers (TMR) Section 13 8-Bit Timers (TMR) This LSI has an on-chip 8-bit timer module with two channels operating on the basis of an 8-bit counter. The 8-bit timer module can be used to count external events and be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers. 13.
PAGE 852
H8S/2456, H8S/2456R, H8S/2454 Group Section 13 8-Bit Timers (TMR) Figure 13.1 shows a block diagram of the 8-bit timer module (TMR_0 and TMR_1).
PAGE 853
H8S/2456, H8S/2456R, H8S/2454 Group 13.2 Section 13 8-Bit Timers (TMR) Input/Output Pins Table 13.1 shows the pin configuration of the 8-bit timer module. Table 13.
PAGE 854
Section 13 8-Bit Timers (TMR) 13.3 H8S/2456, H8S/2456R, H8S/2454 Group Register Descriptions The 8-bit timer module has the following registers. For details on the module stop control register, see section 24.1.2, Module Stop Control Registers H and L (MSTPCRH, MSTPCRL).
PAGE 855
H8S/2456, H8S/2456R, H8S/2454 Group 13.3.1 Section 13 8-Bit Timers (TMR) Timer Counter (TCNT) TCNT is 8-bit up-counter. TCNT_0 and TCNT_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. Bits CKS2 to CKS0 in TCR are used to select a clock. TCNT can be cleared by an external reset input or by a compare match signal A or B. Which signal is to be used for clearing is selected by bits CCLR1 and CCLR0 in TCR.
PAGE 856
H8S/2456, H8S/2456R, H8S/2454 Group Section 13 8-Bit Timers (TMR) 13.3.4 Timer Control Register (TCR) TCR selects the clock source and the time at which TCNT is cleared, and controls interrupts. Bit Bit Name Initial Value R/W Description 7 CMIEB 0 R/W Compare Match Interrupt Enable B Selects whether CMFB interrupt requests (CMIB) are enabled or disabled when the CMFB flag in TCSR is set to 1.
PAGE 857
H8S/2456, H8S/2456R, H8S/2454 Group 13.3.5 Section 13 8-Bit Timers (TMR) Timer Counter Control Register (TCCR) TCCR selects the TCNT internal clock source and controls the external reset input. Bit Bit Name Initial Value R/W Description 7 to 4 ⎯ All 0 R Reserved These bits are always read as 0 and cannot be modified. 3 TMRIS 0 R/W Timer Reset Input Select Selects the external reset input, in combination with the CCLR1 and CCLR0 bits in TCR. See table 13.2.
PAGE 858
H8S/2456, H8S/2456R, H8S/2454 Group Section 13 8-Bit Timers (TMR) Table 13.
PAGE 859
H8S/2456, H8S/2456R, H8S/2454 Group Section 13 8-Bit Timers (TMR) TCR TCCR Channel Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 Bit 1 ICKS1 Bit 0 ICKS0 Description All 1 0 1 ⎯ ⎯ External clock, counted at rising edge 1 0 ⎯ ⎯ External clock, counted at falling edge 1 1 ⎯ ⎯ External clock, counted at both rising and falling edges Note: 13.3.6 * If the count input of TMR_0 is the TCNT_1 overflow signal and that of TMR_1 is the TCNT_0 compare match signal, no incrementing clock is generated.
PAGE 860
H8S/2456, H8S/2456R, H8S/2454 Group Section 13 8-Bit Timers (TMR) Bit Bit Name Initial Value R/W Description 5 OVF 0 R/(W)* Timer Overflow Flag [Setting condition] Set when TCNT overflows from H'FF to H'00 [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 to OVF 4 ADTE 0 R/W A/D Trigger Enable Selects enabling or disabling of A/D converter start requests by compare match A.
PAGE 861
H8S/2456, H8S/2456R, H8S/2454 Group • Section 13 8-Bit Timers (TMR) TCSR_1 Bit Bit Name Initial Value R/W Description 7 CMFB 0 R/(W)* Compare Match Flag B [Setting condition] • Set when TCNT matches TCORB [Clearing conditions] 6 CMFA 0 R/(W)* • Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB • When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0 Compare Match Flag A [Setting condition] • Set when TCNT matches TCORA [Clearing conditions] 5 OVF
PAGE 862
H8S/2456, H8S/2456R, H8S/2454 Group Section 13 8-Bit Timers (TMR) Bit Bit Name Initial Value R/W Description 3 OS3 0 R/W Output Select 3 and 2 2 OS2 0 R/W These bits select a method of TMO pin output when compare match B of TCORB and TCNT occurs.
PAGE 863
H8S/2456, H8S/2456R, H8S/2454 Group 13.4 Operation 13.4.1 Pulse Output Section 13 8-Bit Timers (TMR) Figure 13.2 shows an example in which the 8-bit timer is used to generate a pulse output with a selected duty cycle. The control bits are set as follows: [1] In TCR, the CCLR1 bit is cleared to 0 and the CCLR0 bit is set to 1 so that TCNT is cleared at a TCORA compare match.
PAGE 864
H8S/2456, H8S/2456R, H8S/2454 Group Section 13 8-Bit Timers (TMR) 13.4.2 Reset Input Figure 13.3 shows an example in which the 8-bit timer is used to generate a pulse output with a selected delay in response to the TMRI input. The control bits are set as follows: [1] The CCLR0 bit in TCR is set to 1 and the TMRIS bit in TCCR is set to 1 so that TCNT is cleared at the high level of the TMRI input.
PAGE 865
H8S/2456, H8S/2456R, H8S/2454 Group 13.5 Operation Timing 13.5.1 TCNT Incrementation Timing Section 13 8-Bit Timers (TMR) Figure 13.4 shows the count timing for internal clock input. Figure 13.5 shows the count timing for external clock signal. Note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges. The counter will not increment correctly if the pulse width is less than these values.
PAGE 866
H8S/2456, H8S/2456R, H8S/2454 Group Section 13 8-Bit Timers (TMR) 13.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT match, the compare match signal is not generated until the next incrementation clock input. Figure 13.
PAGE 867
H8S/2456, H8S/2456R, H8S/2454 Group 13.5.4 Section 13 8-Bit Timers (TMR) Timing of Compare Match Clear TCNT is cleared when compare match A or B occurs, depending on the settings of the CCLR1 and CCLR0 bits in TCR and the TMRIS bit in TCCR. Figure 13.8 shows the timing of this operation. φ Compare match signal TCNT N H'00 Figure 13.8 Timing of Compare Match Clear 13.5.
PAGE 868
H8S/2456, H8S/2456R, H8S/2454 Group Section 13 8-Bit Timers (TMR) 13.5.6 Timing of Overflow Flag (OVF) Setting The OVF in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 13.10 shows the timing of this operation. φ TCNT H'FF H'00 Overflow signal OVF Figure 13.10 Timing of OVF Setting Page 838 of 1408 R01UH0309EJ0500 Rev. 5.
PAGE 869
H8S/2456, H8S/2456R, H8S/2454 Group 13.6 Section 13 8-Bit Timers (TMR) Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match count mode). In this case, the timer operates as below. 13.6.
PAGE 870
H8S/2456, H8S/2456R, H8S/2454 Group Section 13 8-Bit Timers (TMR) 13.7 Interrupt Sources 13.7.1 Interrupt Sources and DTC Activation There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are shown in table 13.4. Each interrupt source is set as enabled or disabled by the corresponding interrupt enable bit in TCR or TCSR, and independent interrupt requests are sent for each to the interrupt controller.
PAGE 871
H8S/2456, H8S/2456R, H8S/2454 Group Section 13 8-Bit Timers (TMR) 13.8 Usage Notes 13.8.1 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 13.11 shows this operation. TCNT write cycle by CPU T1 T2 φ Address TCNT address Internal write signal Counter clear signal TCNT N H'00 Figure 13.
PAGE 872
H8S/2456, H8S/2456R, H8S/2454 Group Section 13 8-Bit Timers (TMR) 13.8.2 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 13.12 shows this operation. TCNT write cycle by CPU T1 T2 φ Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 13.
PAGE 873
H8S/2456, H8S/2456R, H8S/2454 Group 13.8.3 Section 13 8-Bit Timers (TMR) Contention between TCOR Write and Compare Match During the T2 state of a TCOR write cycle, the TCOR write has priority and the compare match signal is inhibited even if a compare match event occurs as shown in figure 13.13. TCOR write cycle by CPU T1 T2 φ Address TCOR address Internal write signal TCNT N N+1 TCOR N M TCOR write data Compare match signal Inhibited Figure 13.
PAGE 874
Section 13 8-Bit Timers (TMR) 13.8.4 H8S/2456, H8S/2456R, H8S/2454 Group Contention between Compare Matches A and B If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 13.5. Table 13.5 Timer Output Priorities Output Setting Priority Toggle output High 1 output 0 output No change 13.8.
PAGE 875
H8S/2456, H8S/2456R, H8S/2454 Group Section 13 8-Bit Timers (TMR) Table 13.6 Switching of Internal Clock and TCNT Operation No.
PAGE 876
H8S/2456, H8S/2456R, H8S/2454 Group Section 13 8-Bit Timers (TMR) No. 4 Timing of Switchover by Means of Modifying CKS1, CKS0, ICKS1, and ICKS0 Bits TCNT Clock Operation Switching from high to high Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit write Notes: 1. 2. 3. 4. 13.8.6 Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop.
PAGE 877
H8S/2456, H8S/2456R, H8S/2454 Group Section 14 Watchdog Timer (WDT) Section 14 Watchdog Timer (WDT) The watchdog timer (WDT) is an 8-bit timer that outputs an overflow signal (WDTOVF) if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. At the same time, the WDT can also generate an internal reset signal. When this watchdog function is not needed, the WDT can be used as an interval timer.
PAGE 878
H8S/2456, H8S/2456R, H8S/2454 Group Overflow Interrupt control WOVI (interrupt request signal) Clock WDTOVF Internal reset signal* Clock select Reset control RSTCSR TCNT φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Internal clock sources TSCR Module bus Bus interface Internal bus Section 14 Watchdog Timer (WDT) WDT [Legend] Timer control/status register TCSR: Timer counter TCNT: RSTCSR: Reset control/status register Note: * An internal reset signal can be generated by the register sett
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H8S/2456, H8S/2456R, H8S/2454 Group 14.3 Section 14 Watchdog Timer (WDT) Register Descriptions The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to in a method different from normal registers. For details, refer to section 14.6.1, Notes on Register Access. • • • Timer counter (TCNT) Timer control/status register (TCSR) Reset control/status register (RSTCSR) 14.3.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable up-counter.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 14 Watchdog Timer (WDT) Bit Bit Name Initial Value R/W Description 6 WT/IT 0 R/W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode When TCNT overflows, an interval timer interrupt (WOVI) is requested. 1: Watchdog timer mode When TCNT overflows, the WDTOVF signal is output. 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting.
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H8S/2456, H8S/2456R, H8S/2454 Group 14.3.3 Section 14 Watchdog Timer (WDT) Reset Control/Status Register (RSTCSR) RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by overflows.
PAGE 882
Section 14 Watchdog Timer (WDT) 14.4 Operation 14.4.1 Watchdog Timer Mode H8S/2456, H8S/2456R, H8S/2454 Group To use the WDT as a watchdog timer mode, set the WT/IT and TME bits in TCSR to 1. If TCNT overflows without being rewritten because of a system crash or other error, the WDTOVF signal is output. This ensures that TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflow occurs.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 14 Watchdog Timer (WDT) TCNT count Overflow H'FF Time H'00 WT/IT=1 TME=1 H'00 written to TCNT WOVF=1 WDTOVF and internal reset are generated WT/IT=1 TME=1 H'00 written to TCNT WDTOVF signal 132 states*2 Internal reset signal*1 518 states Notes: 1. If TCNT overflows when the RSTE bit is set to 1, an internal reset signal is generated. 2. 130 states when the RSTE bit is cleared to 0. Figure 14.2 Operation in Watchdog Timer Mode R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 14 Watchdog Timer (WDT) 14.4.2 Interval Timer Mode To use the WDT as an interval timer, set the WT/IT bit to 0 and TME bit in TCSR to 1. When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the same time the OVF bit in the TCSR is set to 1.
PAGE 885
H8S/2456, H8S/2456R, H8S/2454 Group 14.6 Usage Notes 14.6.1 Notes on Register Access Section 14 Watchdog Timer (WDT) The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. (1) Writing to TCNT, TCSR, and RSTCSR TCNT and TCSR must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction.
PAGE 886
H8S/2456, H8S/2456R, H8S/2454 Group Section 14 Watchdog Timer (WDT) TCNT write or Writing to RSTE bit in RSTCSR 15 Address: H'FFBC (TCNT) H'FFBE (RSTCSR) 8 7 H'5A 0 Write data TCSR write Address: H'FFBC (TCSR) 15 8 7 H'A5 0 Write data Writing 0 to WOVF bit in RSTCSR Address: H'FFBE (RSTCSR) 15 8 7 H'A5 0 H'00 Writing to RSTE bit in RSTCSR Address: H'FFBE (RSTCSR) 15 8 H'5A 7 0 Write data Figure 14.
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H8S/2456, H8S/2456R, H8S/2454 Group 14.6.2 Section 14 Watchdog Timer (WDT) Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the next cycle after the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 14.5 shows this operation. TCNT write cycle T1 T2 Next cycle φ Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 14.
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Section 14 Watchdog Timer (WDT) 14.6.5 H8S/2456, H8S/2456R, H8S/2454 Group Internal Reset in Watchdog Timer Mode This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer mode operation, but TCNT and TCSR of the WDT are reset. TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal is low. Also note that a read of the WOVF flag is not recognized during this period.
PAGE 889
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Section 15 Serial Communication Interface (SCI, IrDA) This LSI has five independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication.
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Section 15 Serial Communication Interface (SCI, IrDA) H8S/2456, H8S/2456R, H8S/2454 Group Asynchronous Mode • • • • • Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Receive error detection: Parity, overrun, and framing errors Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error • Average transfer rate generator (SCI_2 only): 115.152, or 460.606 kbps at 10.667-MHz operation 115.196, 460.
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H8S/2456, H8S/2456R, H8S/2454 Group Bus interface Section 15 Serial Communication Interface (SCI, IrDA) Module data bus RxD RDR TDR RSR TSR SCMR SSR SCR SMR SEMR BRR φ Baud rate generator Transmission/ reception control TxD Parity generation φ/4 φ/16 φ/64 Clock Parity check External clock SCK Internal data bus [Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: Serial control register SSR:
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H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) 15.2 Input/Output Pins Table 15.1 shows the pin configuration of the serial communication interface. Table 15.
PAGE 893
H8S/2456, H8S/2456R, H8S/2454 Group 15.3 Section 15 Serial Communication Interface (SCI, IrDA) Register Descriptions The SCI has the following registers. The serial mode register (SMR), serial status register (SSR), and serial control register (SCR) are described separately for normal serial communication interface mode and Smart Card interface mode because their bit functions partially differ.
PAGE 894
Section 15 Serial Communication Interface (SCI, IrDA) • • • • • • • • • • • • • • • • • • H8S/2456, H8S/2456R, H8S/2454 Group Receive shift register_3 (RSR_3) Transmit shift register_3 (TSR_3) Receive data register_3 (RDR_3) Transmit data register_3 (TDR_3) Serial mode register_3 (SMR_3) Serial control register_3 (SCR_3) Serial status register_3 (SSR_3) Smart card mode register_3 (SCMR_3) Bit rate register_3 (BRR_3) Receive shift register_4 (RSR_4) Transmit shift register_4 (TSR_4) Receive data register_
PAGE 895
H8S/2456, H8S/2456R, H8S/2454 Group 15.3.3 Section 15 Serial Communication Interface (SCI, IrDA) Transmit Data Register (TDR) TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structures of TDR and TSR enable continuous serial transmission.
PAGE 896
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting.
PAGE 897
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Smart Card Interface Mode (When SMIF bit in SCMR is 1) Bit Bit Name Initial Value R/W Description 7 GM 0 R/W GSM Mode When this bit is set to 1, the SCI operates in GSM mode. In GSM mode, the timing of the TEND setting is advanced by 11.0 etu (Elementary Time Unit: the time for transfer of 1 bit), and clock output control mode addition is performed. For details, refer to section 15.7.8, Clock Output Control.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 3 BCP1 0 R/W Basic Clock Pulse 1 and 0 2 BCP0 0 R/W These bits, in combination with the BCP2 bit in SCMR, select the number of basic clock cycles in a 1-bit transfer interval in Smart Card interface mode.
PAGE 899
H8S/2456, H8S/2456R, H8S/2454 Group 15.3.6 Section 15 Serial Communication Interface (SCI, IrDA) Serial Control Register (SCR) SCR performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer/receive clock source. For details on interrupt requests, refer to section 15.9, Interrupt Sources. Some bit functions of SCR differ in normal serial communication interface mode and Smart Card interface mode.
PAGE 900
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 4 RE 0 R/W Receive Enable When this bit is set to 1, reception is enabled. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. SMR setting must be performed to decide the transfer format before setting the RE bit to 1.
PAGE 901
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 1 CKE1 0 R/W Clock Enable 1 and 0 0 CKE0 0 R/W Selects the clock source and SCK pin function. Asynchronous mode 00: On-chip baud rate generator SCK pin functions as I/O port 01: On-chip baud rate generator (Outputs a clock of the same frequency as the bit rate from the SCK pin.
PAGE 902
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Smart Card Interface Mode (When SMIF bit in SCMR is 1) Bit Bit Name Initial Value R/W Description 7 TIE 0 R/W Transmit Interrupt Enable When this bit is set to 1, TXI interrupt request is enabled. TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0.
PAGE 903
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 2 TEIE 0 R/W Transmit End Interrupt Enable Write 0 to this bit in Smart Card interface mode. 1 CKE1 0 R/W Clock Enable 1 and 0 0 CKE0 0 R/W Enables or disables clock output from the SCK pin. The clock output can be dynamically switched in GSM mode. For details, refer to section 15.7.8, Clock Output Control.
PAGE 904
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) 15.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit functions of SSR differ in normal serial communication interface mode and Smart Card interface mode.
PAGE 905
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 5 ORER 0 R/(W)* Overrun Error Indicates that an overrun error occurred while receiving and the reception has ended abnormally. [Setting condition] • When the next serial reception is completed while RDRF = 1 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost.
PAGE 906
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 4 FER 0 R/(W)* Framing Error Indicates that a framing error occurred while receiving in asynchronous mode and the reception has ended abnormally. [Setting condition] • When the stop bit is 0 In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked.
PAGE 907
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 2 TEND 1 R Transmit End [Setting conditions] • When the TE bit in SCR is 0 • When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Clearing conditions] 1 MPB 0 R • When 0 is written to TDRE after reading TDRE =1 • When the DMAC or DTC is activated by a TXI interrupt and writes data to TDR Multiprocessor Bit MPB stores the
PAGE 908
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Smart Card Interface Mode (When SMIF bit in SCMR is 1) Bit Bit Name Initial Value R/W Description 7 TDRE 1 R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR, and data writing to TDR is enabled.
PAGE 909
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 5 ORER 0 R/(W)* Overrun Error Indicates that an overrun error occurred while receiving and the reception has ended abnormally. [Setting condition] • When the next serial reception is completed while RDRF = 1 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost.
PAGE 910
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 3 PER 0 R/(W)* Parity Error Indicates that a parity error occurred while receiving in asynchronous mode and the reception has ended abnormally. [Setting condition] • When a parity error is detected during reception If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set.
PAGE 911
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 2 TEND 1 R Transmit End This bit is set to 1 when no error signal has been sent back from the receiving end and the next transmit data is ready to be transferred to TDR.
PAGE 912
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) 15.3.8 Smart Card Mode Register (SCMR) SCMR selects Smart Card interface mode and its format. Bit Bit Name Initial Value R/W Description 7 BCP2 1 R/W Basic Clock Pulse 2 Selects, in combination with the BCP1 and BCP0 bits in SMR, the number of basic clock cycles in a 1-bit transfer interval in Smart Card interface mode. For the settings, refer to section 15.3.5, Serial Mode Register (SMR).
PAGE 913
H8S/2456, H8S/2456R, H8S/2454 Group 15.3.9 Section 15 Serial Communication Interface (SCI, IrDA) Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 15.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode, clocked synchronous mode, and Smart Card interface mode.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Table 15.3 shows sample N settings in BRR in normal asynchronous mode. Table 15.4 shows the maximum bit rate for each frequency in normal asynchronous mode. Table 15.6 shows sample N settings in BRR in clocked synchronous mode. Table 15.8 shows sample N settings in BRR in Smart Card interface mode. In Smart Card interface mode, S (the number of basic clock cycles in a 1-bit transfer interval) can be selected.
PAGE 915
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Operating Frequency φ (MHz) 12.288 14 14.7456 16 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 217 0.08 2 248 –0.17 3 64 0.69 3 70 0.03 150 2 159 0.00 2 181 0.16 2 191 0.00 2 207 0.16 300 2 79 0.00 2 90 0.16 2 95 0.00 2 103 0.16 600 1 159 0.00 1 181 0.16 1 191 0.00 1 207 0.16 1200 1 79 0.00 1 90 0.16 1 95 0.
PAGE 916
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Operating Frequency φ (MHz) 25 30 33 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) 110 3 110 –0.02 3 132 0.13 3 145 0.33 150 3 80 0.47 3 97 –0.35 3 106 0.39 300 2 162 –0.15 2 194 0.16 2 214 –0.07 600 2 80 0.47 2 97 –0.35 2 106 0.39 1200 1 162 –0.15 1 194 0.16 1 214 –0.07 2400 1 80 0.47 1 97 –0.35 1 106 0.39 4800 0 162 –0.
PAGE 917
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Table 15.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ (MHz) Maximum Bit Rate (bit/s) n N 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 19.
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Section 15 Serial Communication Interface (SCI, IrDA) H8S/2456, H8S/2456R, H8S/2454 Group Table 15.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.6864 230400 16 4.0000 250000 17.2032 4.3008 268800 18 4.5000 281250 19.6608 4.9152 307200 20 5.0000 312500 25 6.
PAGE 919
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ (MHz) Bit Rate (bit/s) n 8 10 16 N n N n N 20 n N 25 n N 30 n N 3 233 33 n N 110 250 3 124 ⎯ ⎯ 3 249 500 2 249 ⎯ ⎯ 3 124 ⎯ ⎯ 1k 2 124 ⎯ ⎯ 2 249 ⎯ ⎯ 3 97 3 116 3 128 2.
PAGE 920
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Table 15.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (when n = 0 and S = 372) Operating Frequency φ (MHz) 10.00 10.7136 13.00 14.2848 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 9600 0 1 30.00 0 1 25.00 0 1 8.99 0 1 0.00 Operating Frequency φ (MHz) 16.00 18.00 20.00 25.
PAGE 921
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) 15.3.10 IrDA Control Register (IrCR) IrCR selects the function of SCI_0. Bit Bit Name Initial Value R/W Description 7 IrE 0 R/W IrDA Enable Specifies normal SCI mode or IrDA mode for SCI_0 input/output.
PAGE 922
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 2 IrRxINV 0 R/W IrRx Data Invert Specifies the logic level of the IrRxD output to be inverted. When inversion is performed, the high pulse width specified by bits 6 to 4 becomes the low pulse width.
PAGE 923
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 2 ACS2 0 R/W 1 ACS1 0 R/W Asynchronous clock source selection (valid when CKE1 = 1 in asynchronous mode) 0 ACS0 0 R/W Selects the clock source for the average transfer rate. The basic clock can be automatically set by selecting the average transfer rate in spite of the value of ABCS. 000: External clock input 001: Selects 115.
PAGE 924
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) 15.4 Operation in Asynchronous Mode Figure 15.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transfer data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level).
PAGE 925
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Table 15.
PAGE 926
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization.
PAGE 927
H8S/2456, H8S/2456R, H8S/2454 Group 15.4.3 Section 15 Serial Communication Interface (SCI, IrDA) Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used.
PAGE 928
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) 15.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 15.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is cleared to 0, the TDRE flag is set to 1.
PAGE 929
H8S/2456, H8S/2456R, H8S/2454 Group 15.4.5 Section 15 Serial Communication Interface (SCI, IrDA) Data Transmission (Asynchronous Mode) Figure 15.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2.
PAGE 930
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Initialization [1] Start of transmission Read TDRE flag in SSR [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
PAGE 931
H8S/2456, H8S/2456R, H8S/2454 Group 15.4.6 Section 15 Serial Communication Interface (SCI, IrDA) Serial Data Reception (Asynchronous Mode) Figure 15.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2.
PAGE 932
Section 15 Serial Communication Interface (SCI, IrDA) H8S/2456, H8S/2456R, H8S/2454 Group Table 15.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.9 shows a sample flowchart for serial data reception.
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H8S/2456, H8S/2456R, H8S/2454 Group Initialization Section 15 Serial Communication Interface (SCI, IrDA) [1] Start of reception [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error handling and break detection: Read ORER, PER, and If a receive error occurs, read the [2] FER flags in SSR ORER, PER, and FER flags in SSR to identify the error.
PAGE 934
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) [3] Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Yes Break? No Framing error handling Clear RE bit in SCR to 0 No PER = 1? Yes Parity error handling Clear ORER, PER, and FER flags in SSR to 0 Figure 15.9 Sample Serial Reception Data Flowchart (2) Page 904 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group 15.5 Section 15 Serial Communication Interface (SCI, IrDA) Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Transmitting station Serial communication line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB= 1) ID transmission cycle = receiving station specification (MPB= 0) Data transmission cycle = data transmission to receiving station specified by ID Legend: MPB: Multiprocessor bit Figure 15.
PAGE 937
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) [1] [1] SCI initialization: Initialization Start of transmission Read TDRE flag in SSR [2] No TDRE = 1? Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 No All data transmitted? Yes Read TEND flag in SSR No The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled.
PAGE 938
Section 15 Serial Communication Interface (SCI, IrDA) 15.5.2 H8S/2456, H8S/2456R, H8S/2454 Group Multiprocessor Serial Data Reception Figure 15.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time.
PAGE 939
H8S/2456, H8S/2456R, H8S/2454 Group 1 Start bit 0 Section 15 Serial Communication Interface (SCI, IrDA) Data (ID1) MPB D0 D1 D7 1 Stop bit Start bit 1 0 Data (Data1) MPB D0 D1 D7 0 Stop bit 1 1 Idle state (mark state) MPIE RDRF RDR value ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine If not this station’s ID, RXI interrupt request is MPIE bit is set to 1 not generated, and RDR again
PAGE 940
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Initialization [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [2] ID reception cycle: Set the MPIE bit in SCR to 1.
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H8S/2456, H8S/2456R, H8S/2454 Group [5] Section 15 Serial Communication Interface (SCI, IrDA) Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Yes Break? No Framing error handling Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2) R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) 15.6 Operation in Clocked Synchronous Mode Figure 15.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character of communication data consists of 8-bit data. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next.
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H8S/2456, H8S/2456R, H8S/2454 Group 15.6.2 Section 15 Serial Communication Interface (SCI, IrDA) SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 15.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is cleared to 0, the TDRE flag is set to 1.
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Section 15 Serial Communication Interface (SCI, IrDA) 15.6.3 H8S/2456, H8S/2456R, H8S/2454 Group Serial Data Transmission (Clocked Synchronous Mode) Figure 15.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Transfer direction Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated Data written to TDR TXI interrupt and TDRE flag request generated cleared to 0 in TXI interrupt handling routine TEI interrupt request generated 1 frame Figure 15.16 Sample SCI Transmission Operation in Clocked Synchronous Mode R01UH0309EJ0500 Rev. 5.
PAGE 946
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Initialization [1] Start of transmission Read TDRE flag in SSR [2] No TDRE = 1? Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? [3] Yes Read TEND flag in SSR [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin.
PAGE 947
H8S/2456, H8S/2456R, H8S/2454 Group 15.6.4 Section 15 Serial Communication Interface (SCI, IrDA) Serial Data Reception (Clocked Synchronous Mode) Figure 15.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the received data in RSR. 2.
PAGE 948
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Initialization [1] Start of reception [2] Read ORER flag in SSR Yes [3] ORER = 1? No Error processing (Continued below) Read RDRF flag in SSR [4] No RDRF = 1? Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 [5] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin.
PAGE 949
H8S/2456, H8S/2456R, H8S/2454 Group 15.6.5 Section 15 Serial Communication Interface (SCI, IrDA) Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 15.20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations after the SCI is initialized.
PAGE 950
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Initialization [1] SCI initialization: [1] The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations.
PAGE 951
H8S/2456, H8S/2456R, H8S/2454 Group 15.7 Section 15 Serial Communication Interface (SCI, IrDA) Operation in Smart Card Interface Mode The SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting. 15.7.1 Pin Connection Example Figure 15.
PAGE 952
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) 15.7.2 Data Format (Except for Block Transfer Mode) Figure 15.22 shows the transfer data format in Smart Card interface mode. • One frame consists of 8-bit data plus a parity bit in asynchronous mode. • In transmission, a guard time of at least 2 etu (Elementary Time Unit: time for transfer of 1 bit) is left between the end of the parity bit and the start of the next frame.
PAGE 953
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) As in the above sample start character, with the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. For the direct convention type, clear the SDIR and SINV bits in SCMR to 0. According to the Smart Card regulations, clear the O/E bit in SMR to 0 to select even parity mode.
PAGE 954
Section 15 Serial Communication Interface (SCI, IrDA) 15.7.4 H8S/2456, H8S/2456R, H8S/2454 Group Receive Data Sampling Timing and Reception Margin Only the internal clock generated by the on-chip baud rate generator is used as transmit/receive clock in Smart Card interface. In Smart Card interface mode, the SCI operates on a basic clock with a frequency of 32, 64, 372, 256, 93, 128, 186, or 512 times the bit rate (fixed at 16 times in normal asynchronous mode) as determined by bits BCP2 to BCP0.
PAGE 955
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) 372 clocks 186 clocks 0 185 185 371 0 371 0 Internal basic clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 15.25 Receive Data Sampling Timing in Smart Card Mode (Using Clock of 372 Times the Bit Rate) R01UH0309EJ0500 Rev. 5.
PAGE 956
Section 15 Serial Communication Interface (SCI, IrDA) 15.7.5 H8S/2456, H8S/2456R, H8S/2454 Group Initialization Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. Clear the TE and RE bits in SCR to 0. 2. Clear the error flags ERS, PER, and ORER in SSR to 0. 3. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR, and the BCP2 bit in SCMR. Set the PE bit to 1. 4.
PAGE 957
H8S/2456, H8S/2456R, H8S/2454 Group 15.7.6 Section 15 Serial Communication Interface (SCI, IrDA) Data Transmission (Except for Block Transfer Mode) As data transmission in Smart Card interface mode involves error signal sampling and retransmission processing, the operations are different from those in normal serial communication interface mode (except for block transfer mode). Figure 15.26 illustrates the retransfer operation when the SCI is in transmit mode. 1.
PAGE 958
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Transfer frame n+1 Retransferred frame nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Ds D0 D1 D2 D3 D4 TDRE Transfer to TSR from TDR Transfer to TSR from TDR Transfer to TSR from TDR TEND [2] [4] FER/ERS [1] [3] Figure 15.26 Retransfer Operation in SCI Transmit Mode The timing for setting the TEND flag depends on the value of the GM bit in SMR.
PAGE 959
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Start Initialization Start transmission ERS = 0? No Yes Error processing No TEND = 1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No All data transmitted ? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit to 0 End Figure 15.28 Example of Transmission Processing Flow R01UH0309EJ0500 Rev. 5.
PAGE 960
Section 15 Serial Communication Interface (SCI, IrDA) 15.7.7 H8S/2456, H8S/2456R, H8S/2454 Group Serial Data Reception (Except for Block Transfer Mode) Data reception in Smart Card interface mode uses the same operation procedure as for normal serial communication interface mode. Figure 15.29 illustrates the retransfer operation when the SCI is in receive mode. 1. If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1.
PAGE 961
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) nth transfer frame Transfer frame n+1 Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Ds D0 D1 D2 D3 D4 RDRF [2] [4] [1] [3] PER Figure 15.29 Retransfer Operation in SCI Receive Mode R01UH0309EJ0500 Rev. 5.
PAGE 962
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Start Initialization Start reception ORER = 0 and PER = 0 No Yes Error processing No RDRF = 1? Yes Read RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit to 0 Figure 15.30 Example of Reception Processing Flow Page 932 of 1408 R01UH0309EJ0500 Rev. 5.
PAGE 963
H8S/2456, H8S/2456R, H8S/2454 Group 15.7.8 Section 15 Serial Communication Interface (SCI, IrDA) Clock Output Control When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE1 and CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width. Figure 15.31 shows the timing for fixing the clock output level. In this example, GM is set to 1, CKE1 is cleared to 0, and the CKE0 bit is controlled.
PAGE 964
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) When Changing from Smart Card Interface Mode to Software Standby Mode: 1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the value for the fixed output state in software standby mode. 2. Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive operation.
PAGE 965
H8S/2456, H8S/2456R, H8S/2454 Group 15.8 Section 15 Serial Communication Interface (SCI, IrDA) IrDA Operation When the IrDA function is enabled with bit IrE in IrCR, the SCI_0 TxD0 and RxD0 signals are subjected to waveform encoding/decoding conforming to IrDA specification version 1.0 (IrTxD and IrRxD pins). By connecting these pins to an infrared transceiver/receiver, it is possible to implement infrared transmission/reception conforming to the IrDA specification version 1.0 system.
PAGE 966
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) (1) Transmission In transmission, the output signal (UART frame) from the SCI is converted to an IR frame by the IrDA interface (see figure 15.34). When the serial data is 0, a high pulse of 3/16 the bit rate (interval equivalent to the width of one bit) is output (initial value). The high-level pulse can be varied according to the setting of bits IrCKS2 to IrCKS0 in IrCR.
PAGE 967
H8S/2456, H8S/2456R, H8S/2454 Group (2) Section 15 Serial Communication Interface (SCI, IrDA) Reception In reception, IR frame data is converted to a UART frame by the IrDA interface, and input to the SCI. When a high pulse is detected, 0 data is output, and if there is no pulse during a one-bit interval, 1 data is output. Note that a pulse shorter than the minimum pulse width of 1.41 µs will be identified as a 0 signal. (3) High Pulse Width Selection Table 15.
PAGE 968
Section 15 Serial Communication Interface (SCI, IrDA) H8S/2456, H8S/2456R, H8S/2454 Group 15.9 Interrupt Sources 15.9.1 Interrupts in Normal Serial Communication Interface Mode Table 15.13 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated.
PAGE 969
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Table 15.
PAGE 970
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) 15.9.2 Interrupts in Smart Card Interface Mode Table 15.14 shows the interrupt sources in Smart Card interface mode. The transmit end interrupt (TEI) request cannot be used in this mode. Table 15.
PAGE 971
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) When performing transfer using the DTC or DMAC, it is essential to set and enable the DTC or DMAC before carrying out SCI setting. For details on the DTC or DMAC setting procedures, refer to section 9, Data Transfer Controller (DTC) or section 7, DMA Controller (DMAC). In receive operations, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1.
PAGE 972
Section 15 Serial Communication Interface (SCI, IrDA) 15.10 H8S/2456, H8S/2456R, H8S/2454 Group Usage Notes 15.10.1 Module Stop Function Setting SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing the module stop state. For details, refer to section 24, Power-Down Modes. 15.10.
PAGE 973
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) 15.10.5 Relation between Writes to TDR and the TDRE Flag The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR regardless of the state of the TDRE flag.
PAGE 974
Section 15 Serial Communication Interface (SCI, IrDA) H8S/2456, H8S/2456R, H8S/2454 Group 15.10.7 Operation in Case of Mode Transition (1) Transmission Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before setting the module stop state or making a transition to software standby mode. TSR, TDR, and SSR are reset. The output pin states in the module stop state or software standby mode depend on the port settings, and become high-level output after the relevant mode is cleared.
PAGE 975
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Figure 15.39 shows a sample flowchart for mode transition during reception. All data transmitted? No [1] Yes Read TEND flag in SSR TEND = 1 No Yes TE = 0 [2] Transition to software standby mode [3] [1] Data being transmitted is interrupted.
PAGE 976
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) End of transmission Start of transmission Transition to software standby Exit from software standby TE bit Port input/output SCK output pin TxD output pin Port input/output High output Port Start Stop Port input/output SCI TxD output High output SCI TxD output Port Figure 15.
PAGE 977
H8S/2456, H8S/2456R, H8S/2454 Group Section 15 Serial Communication Interface (SCI, IrDA) Read RDRF flag in SSR RDRF = 1 No [1] [1] Receive data being received becomes invalid. [2] [2] Includes setting of module stop state. Yes Read receive data in RDR RE = 0 Transition to software standby mode Exit from software standby mode Change operating mode? No Yes Initialization RE = 1 Figure 15.
PAGE 978
Section 15 Serial Communication Interface (SCI, IrDA) Page 948 of 1408 H8S/2456, H8S/2456R, H8S/2454 Group R01UH0309EJ0500 Rev. 5.
PAGE 979
H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) Section 16 USB Function Module (USB) This LSI incorporates a USB function module (USB). 16.1 Features • The protocol block conforming to USB2.0 and transceiver process USB protocol automatically.
PAGE 980
H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) Figure 16.1 shows the block diagram of the USB. Peripheral bus USB function module Status/control registers Interrupt requests Protocol processing block D+ Transceiver D- FIFO Clock for USB (48 MHz) Figure 16.1 Block Diagram of USB 16.2 Input/Output Pins Table 16.1 shows the USB pin configuration. Table 16.
PAGE 981
H8S/2456, H8S/2456R, H8S/2454 Group 16.3 Section 16 USB Function Module (USB) Register Descriptions The USB has following registers. For the information on the addresses of these registers and the state of the register in each processing condition, see section 25, List of Registers.
PAGE 982
H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) • Transceiver test register 0 (TRNTREG0) • Transceiver test register 1 (TRNTREG1) 16.3.1 Interrupt Flag Register 0 (IFR0) IFR0, together with interrupt flag registers 1 and 2 (IFR1 and IFR2), indicates interrupt status information required by the application. When an interrupt source is generated, the corresponding bit is set to 1.
PAGE 983
H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) Bit Bit Name Initial Value R/W Description 2 SETI 0 R/W Set_Interface Command Detection When the Set_Interface command is detected, this bit is set to 1. 1 VBUSMN 0 R VBUS Pin State Monitor This is a status bit that monitors the state of the VBUS pin. 0: VBUS pin = 0 1: VUBS pin = 1 This is a status bit and cannot be cleared. It generates no interrupt request. This bit is always 0 when the PULLUPE bit in CTLR is 0.
PAGE 984
H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) 16.3.2 Interrupt Flag Register 1 (IFR1) IFR1, together with interrupt flag registers 0 and 2 (IFR0 and IFR2), indicates interrupt status information required by the application. When an interrupt source is generated, the corresponding bit is set to 1. And then this bit, in combination with interrupt enable register 1 (IER1), generates an interrupt request to the CPU.
PAGE 985
H8S/2456, H8S/2456R, H8S/2454 Group 16.3.3 Section 16 USB Function Module (USB) Interrupt Flag Register 2 (IFR2) IFR2, together with interrupt flag registers 0 and 1, (IFR0 and IFR1), indicates interrupt status information required by the application. When an interrupt source is generated, the corresponding bit is set to 1. And then this bit, in combination with interrupt enable register 2 (IER2), generates an interrupt request to the CPU.
PAGE 986
H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) Bit Bit Name Initial Value R/W Description 0 EP1 FULL 0 R EP1 FIFO Full This bit is set when endpoint 1 receives one packet of data successfully from the host, and holds a value of 1 as long as there is valid data in the FIFO buffer. This is a status bit and cannot be cleared. 16.3.4 Interrupt Enable Register 0 (IER0) IER0 enables the interrupt requests of interrupt flag register 0 (IFR0).
PAGE 987
H8S/2456, H8S/2456R, H8S/2454 Group 16.3.5 Section 16 USB Function Module (USB) Interrupt Enable Register 1 (IER1) IER1 enables the interrupt requests of interrupt flag register 1 (IFR1). When an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the CPU. The interrupt vector number is determined by the contents of interrupt select register 1 (ISR1).
PAGE 988
H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) 16.3.6 Interrupt Enable Register 2 (IER2) IER2 enables the interrupt requests of interrupt flag register 2 (IFR2). When an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the CPU. The interrupt vector number is determined by the contents of interrupt select register 2 (ISR2).
PAGE 989
H8S/2456, H8S/2456R, H8S/2454 Group 16.3.7 Section 16 USB Function Module (USB) Interrupt Select Register 0 (ISR0) ISR0 selects the vector numbers of the interrupt requests indicated in interrupt flag register 0 (IFR0). If the USB issues an interrupt request to the INTC when a bit in ISR0 is cleared to 0, the interrupt corresponding to the bit will be USBINTN2. If the USB issues an interrupt request to the INTC when a bit in ISR0 is set to 1, the corresponding interrupt will be USBINTN3.
PAGE 990
H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) 16.3.8 Interrupt Select Register 1 (ISR1) ISR1 selects the vector numbers of the interrupt requests indicated in interrupt flag register 1 (IFR1). If the USB issues an interrupt request to the INTC when a bit in ISR1 is cleared to 0, the interrupt corresponding to the bit will be USBINTN2. If the USB issues an interrupt request to the INTC when a bit in ISR1 is set to 1, the corresponding interrupt will be USBINTN3.
PAGE 991
H8S/2456, H8S/2456R, H8S/2454 Group 16.3.9 Section 16 USB Function Module (USB) Interrupt Select Register 2 (ISR2) ISR2 selects the vector numbers of the interrupt requests indicated in interrupt flag register 2 (IFR2). If the USB issues an interrupt request to the INTC when a bit in ISR2 is cleared to 0, the interrupt corresponding to the bit will be USBINTN2. If the USB issues an interrupt request to the INTC when a bit in ISR2 is set to 1, the corresponding interrupt will be USBINTN3.
PAGE 992
H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) 16.3.11 EP0o Data Register (EPDR0o) EPDR0o is a 16-byte receive FIFO buffer for endpoint 0. EPDR0o holds endpoint 0 receive data other than setup commands. When data is received successfully, EP0o TS in interrupt flag register 1 is set, and the number of receive bytes is indicated in the EP0o receive data size register. After the data has been read, setting EP0o RDFN in trigger register 0 enables the next packet to be received.
PAGE 993
H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) 16.3.13 EP1 Data Register (EPDR1) EPDR1 is a 128-byte receive FIFO buffer for endpoint 1. EPDR1 has a dual-buffer configuration, and has a capacity of twice the maximum packet size. When one packet of data is received successfully, EP1 FULL in interrupt flag register 2 is set, and the number of receive bytes is indicated in the EP1 receive data size register.
PAGE 994
H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) 16.3.15 EP3 Data Register (EPDR3) EPDR3 is a 16-byte transmit FIFO buffer for endpoint 3. EPDR3 holds one packet of transmit data for the interrupt transfer of endpoint 3. Transmit data is fixed by writing one packet of data and setting EP3 PKTE in trigger register 1. This FIFO buffer can be initialized by means of EP3 CLR in FCLR register 1.
PAGE 995
H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) 16.3.18 Data Status Register 0 (DASTS0) DASTS0 indicates whether the transmit FIFO buffers contain valid data. A bit is set when data is written to the corresponding FIFO buffer and the packet enable state is set, and cleared when all data has been transmitted to the host. Bit Bit Name Initial Value R/W Description 7 ⎯ 0 ⎯ Reserved 6 ⎯ 0 ⎯ 5 ⎯ 0 ⎯ These bits are always read as 0. The write value should always be 0.
PAGE 996
H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) 16.3.19 Data Status Register 1 (DASTS1) DASTS1 indicates whether the transmit FIFO buffers contain valid data. A bit is set when data is written to the corresponding FIFO buffer and the packet enable state is set, and cleared when all data has been transmitted to the host. Bit Bit Name Initial Value R/W Description 7 ⎯ 0 ⎯ Reserved 6 ⎯ 0 ⎯ 5 ⎯ 0 ⎯ These bits are always read as 0. The write value should always be 0.
PAGE 997
H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) 16.3.20 Trigger Register 0 (TRG0) TRG0 generates one-shot triggers to control the transfer sequence for endpoint 0. Bit Bit Name Initial Value R/W Description 7 ⎯ 0 ⎯ Reserved 6 ⎯ 0 ⎯ 5 ⎯ 0 ⎯ These bits are always read as 0. The write value should always be 0. 4 ⎯ 0 ⎯ 3 ⎯ 0 ⎯ 2 EP0s RDFN 0 W EP0s Read Complete Write 1 to this bit after data for the EP0s command FIFO has been read.
PAGE 998
H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) 16.3.21 Trigger Register 1 (TRG1) TRG1 generates one-shot triggers to control the transfer sequence for each endpoint. Bit Bit Name Initial Value R/W Description 7 ⎯ 0 ⎯ Reserved 6 ⎯ 0 ⎯ 5 ⎯ 0 ⎯ These bits are always read as 0. The write value should always be 0.
PAGE 999
H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) 16.3.22 FIFO Clear Register 0 (FCLR0) FCLR0 is a register to initialize the FIFO buffers for endpoint 0. Writing 1 to a bit clears all the data in the corresponding FIFO buffer. Note that the corresponding interrupt flag is not cleared. Do not clear a FIFO buffer during transfer. Bit Bit Name Initial Value R/W Description 7 ⎯ 0 ⎯ Reserved 6 ⎯ 0 ⎯ The write value should always be 0.
PAGE 1000
H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) 16.3.23 FIFO Clear Register 1 (FCLR1) FCLR1 is a register to initialize the FIFO buffers for each endpoint. Writing 1 to a bit clears all the data in the corresponding FIFO buffer. Note that the corresponding interrupt flag is not cleared. Do not clear a FIFO buffer during transfer. Bit Bit Name Initial Value R/W Description 7 ⎯ 0 ⎯ Reserved 6 ⎯ 0 ⎯ The write value should always be 0.
PAGE 1001
H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) 16.3.24 Endpoint Stall Register 0 (EPSTL0) Bit 0 in EPSTL0 is used to forcibly stall endpoint 0 on the application side. While the bit is set to 1, the corresponding endpoint returns a stall handshake to the host. Bit 4 is used to clear the stall setting in bit 0. Writing 1 to the EP0 stall setting bit and stall clear bit at the same time is prohibited.
PAGE 1002
H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) 16.3.25 Endpoint Stall Register 1 (EPSTL1) Bits 2 to 0 in EPSTL1 are used to forcibly stall the corresponding endpoints on the application side. While a bit is set to 1, the corresponding endpoint returns a stall handshake to the host. Bits 6 to 4 are used to clear the stall settings for the endpoints (bits 2 to 0). Writing 1 to the stall setting bit and stall clear bit for an endpoint at the same time is prohibited.
PAGE 1003
H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) 16.3.26 Stall Status Register 1 (STLSR1) Bits 2 to 0 in STLSR1 are status bits that indicate the internal stall state of each endpoint (internal status bits shown in figures 16.19 and 16.20). When a bit is 1, the corresponding endpoint is in stall state. When a bit is 0, the corresponding endpoint is in normal operation state. Since these bits are status bits, they cannot be cleared.
PAGE 1004
H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) Bit Bit Name Initial Value R/W Description 3 ⎯ 0 ⎯ Reserved This bit is always read as 0. The write value should always be 0. 2 EP3 STLST 0 R EP3 internal stall state 1 EP2 STLST 0 R EP2 internal stall state 0 EP1 STLST 0 R EP1 internal stall state 16.3.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) Bit Bit Name Initial Value R/W Description 1 EP2 DMAE 0 R/W EP2 DMA Transfer Enable When this bit is set, DMA transfer is enabled from memory to the endpoint 2 transmit FIFO buffer. If there is at least one byte of open space in the FIFO buffer, a DMA transfer request signal (USB INTN1) is asserted.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) Bit Bit Name Initial Value R/W Description 0 EP1 DMAE 0 R/W EP1 DMA Transfer Enable When this bit is set, a DMA transfer request (USB INTN0) is asserted and DMA transfer is enabled from the endpoint 1 receive FIFO buffer to memory. If there is at least one byte of receive data in the FIFO buffer, the DMA transfer request (USB INTN0) is asserted.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) 16.3.28 Configuration Value Register (CVR) This register stores the Configuration, Interface, or Alternate set value when the Set Configuration or Set Interface command from the host is correctly received. Bit Bit Name Initial Value R/W Description 7 CNFV1 All 0 R 6 CNFV0 These bits store Configuration Setting value when they receive Set Configuration command. CNFV is updated when the SETC bit in IFR0 is set to 1.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) Bit Bit Name Initial Value R/W Description 4 RWUPS 0 R Remote Wakeup Status This status bit indicates remote wakeup command from USB host is enabled or disabled. This bit is set to 0 when remote wakeup command from UBM host is disabled by Device_Remote_Wakeup due to Set Feature or Clear Feature request. This bit is set to 1 when remote wakeup command is enabled.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) 16.3.30 Endpoint Information Register (EPIR) This register sets the information for each endpoint. Each endpoint needs five bytes to store the information. Writing data should be done in sequence starting at logical endpoint 0. Make sure to write data of 20 bytes (five bytes multiplied by four endpoints) to this register.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) • EPIR01 Bit Bit Name Initial Value R/W Description 7, 6 D7, D6 Undefined W Endpoint Alternate Number [Possible setting range] 0 5, 4 D5, D4 Undefined W Endpoint Transmission [Possible setting range] 0: Control 1: Setting prohibited 2: Bulk 3: Interrupt 3 D3 Undefined W Endpoint Transmission Direction [Possible setting range] 0: Out 1: In 2 to 0 D2 to D0 Undefined W Reserved [Possible setting range] Fixed to 0
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H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) • EPIR04 Bit Bit Name Initial Value R/W Description 7 to 0 D7 to D0 Undefined W Endpoint FIFO Number [Possible setting range] 0 to 3 The endpoint number is the endpoint number the USB host uses. The endpoint FIFO number corresponds to the endpoint number described in this manual.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) Table 16.2 Limitations for Setting Values Endpoint FIFO Number Maximum Packet Size Transfer Method Transfer Direction 0 16 bytes Control In/Out 1 64 bytes Bulk Out 2 64 bytes Bulk In 3 16 bytes Interrupt In Table 16.3 shows a specific example of setting. Table 16.3 Example of Setting Endpoint Number Conf. Int. Alt.
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H8S/2456, H8S/2456R, H8S/2454 Group 16.3.31 Section 16 USB Function Module (USB) Transceiver Test Register 0 (TRNTREG0) TRNTREG0 controls the on-chip transceiver output signals. Setting the PTSTE bit to 1 specifies the transceiver output signals (USD+ and USD-) arbitrarily. Table 16.4 shows the relationship between TRNTREG0 setting and pin output.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) 16.3.32 Transceiver Test Register 1 (TRNTREG1) TRNTREG1 is a test register that can monitor the on-chip transceiver input signal. Setting bits PTSTE and txenl in TRNTREG0 to 1 enables monitoring the on-chip transceiver input signal. Table 16.5 shows the relationship between pin input and TRNTREG1 monitoring value. Bit Bit Name Initial Value R/W Description 7 to 3 ⎯ All 0 ⎯ Reserved These bits are always read as 0.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) Table 16.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) 16.4 Interrupt Sources This module has five interrupt signals. Table 16.6 shows the interrupt sources and their corresponding interrupt request signals. The USBINTN interrupt signals are activated at low level. The USBINTN interrupt requests can only be detected at low level (specified as level sensitive). Table 16.
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H8S/2456, H8S/2456R, H8S/2454 Group Transfer Mode Interrupt Source Description 0 Bulk_out transfer (EP1) EP1_FULL EP1 FIFO full USBINTN2 or USBINTN3 USBINTN0 (DREQ0) 1 Bulk_in transfer (EP2) EP2_ALLEMP EP2 FIFO all empty USBINTN2 or USBINTN3 x EP2_EMPTY EP2 FIFO empty USBINTN2 or USBINTN3 USBINTN1 (DREQ1) 3 EP2_TR EP2 transfer request USBINTN2 or USBINTN3 x 4 EP3 transmission complete USBINTN2 or USBINTN3 x 5 Interrupt_in EP3_TS transfer (EP3) EP3_TR EP3 transfer request USBINTN2
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Section 16 USB Function Module (USB) 16.5 Operation 16.5.1 Initial Settings USB function H8S/2456, H8S/2456R, H8S/2454 Group Application Power-on reset state canceled 48-MHz USB clock supply started Set the multiplication ratio for the USB PLL frequency. (USSTC1 and USSTC0 in USPLLCR) With a software timer, and so on, wait for 48-MHz USB clock oscillation to be settled. (tUSOSC) Cancel 48-MHz USB clock module stop mode. (Clear MSTP17 in EXMSTPCRL to 0.) Cancel USB system clock module stop mode.
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H8S/2456, H8S/2456R, H8S/2454 Group 16.5.2 Section 16 USB Function Module (USB) Cable Connection USB function Application Cable disconnected VBUS pin = 0 V Protocol processing block reset USB module interrupt setting Initial settings As soon as preparations are completed, enable D+ pull-up. USB cable connection No General output port D+ pull-up enabled? Yes Interrupt request IFR0.
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Section 16 USB Function Module (USB) 16.5.3 H8S/2456, H8S/2456R, H8S/2454 Group Cable Disconnection USB function Application Cable connected VBUS pin = 1 USB cable disconnection VBUS pin = 0 Protocol processing block reset End Figure 16.4 Cable Disconnection Operation The above flowchart shows the operation in section 16.9, Example of USB External Circuitry. Page 990 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group 16.5.4 (1) Section 16 USB Function Module (USB) Suspend and Resume Operations Suspend Operation If the USB bus enters the suspend state from the non-suspend state, perform the operation as shown in figure 16.5. R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) Application USB function USB cable connected Bus idle of 3 ms or more occurs Suspend/resume interrupt occurs. (IFR0/SURSF = 1) USBINTN2 or USBINTN3 Clear SURSF in IFR0 to 0. Check if SURSS in IFR0 is set to 1. Remote wakeup enabled? (CTLR/RWUPS = 1?) N Y Check remote-wakeup function enabled. Check remote-wakeup function disabled.
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H8S/2456, H8S/2456R, H8S/2454 Group (2) Section 16 USB Function Module (USB) Resume Operation from Up-Stream If the USB bus enters the non-suspend state from the suspend state by resume signal output from up-stream, perform the operation as shown in figure 16.6. Application USB function USB cable connected USB bus in suspend state Resume interrupt is requested from the up-stream. Suspend/resume interrupt occurs.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) (3) Transition from Suspend State to Software Standby Mode and Canceling Software Standby Mode If the USB bus enters from the suspend state to software standby mode, perform the operation as shown in figure 16.7. When canceling software standby mode, ensure enough time for the system clock oscillation to be settled.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) (10) (1) USB bus state Normal Resume → Normal Suspend (3) USBINTN interrupt IFR0/SURSF IFR0/SURSS (2) (4) (15) (4) (15) IER0/SURSFE (5) (16) IER0/SSRSME (5) (16) RESUME interrupt EXMSTPCRL/ MSTP17 Software standby (11) (6) (13) (12) (8) Oscillator (9) Software standby Oscillation settling time (tOSC2) (9) System clock (φ) (9) PLL USB clock Two cycles of 48-MHz USB clock 48-MHz USB clock (cku) (7) T
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Section 16 USB Function Module (USB) (4) H8S/2456, H8S/2456R, H8S/2454 Group Remote-Wakeup Operation If the USB bus enters the non-suspend (resume) state from the suspend state by the remotewakeup signal output from this function, perform the operation as shown in figure 16.9. Page 996 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) Application USB function USB cable connected USB bus in suspend state Remote wakeup enabled? (CTLR/RWUPS = 1?) N Y Bus wakeup source generated Wait for resume from up-stream Y Software standby mode ? Cancel software standby mode N Oscillation stabilization time has passed? N Y 48-MHz USB clock supply started Cancel 48-MHz USB clock module stop. (Clear MSTP17 in EXMSTPCRL to 0) Set SURSFE in IER0 to 1.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) 16.5.5 Control Transfer Control transfer consists of three stages: setup, data (not always included), and status (figure 16.10). The data stage comprises a number of bus transactions. Operation flowcharts for each stage are shown below. Setup stage Control-in Control-out No data Data stage SETUP(0) IN(1) IN(0) DATA0 DATA1 DATA0 SETUP(0) OUT(1) OUT(0) DATA0 DATA1 DATA0 Status stage ... ...
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H8S/2456, H8S/2456R, H8S/2454 Group (1) Section 16 USB Function Module (USB) Setup Stage Application USB function SETUP token reception Receive 8-byte command data in EP0s Command to be processed by application? No Automatic processing by this module Yes Set setup command reception complete flag. (IFR1.SETUP TS = 1) To data stage Interrupt request Clear SETUP TS flag. (IFR1.SETUP TS = 0) Clear EP0i FIFO. (FCLR0.EP0iCLR = 1) Clear EP0o FIFO..(FCLR0.EP0oCLR = 1) Read 8-byte data from EP0s.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) (2) Data Stage (Control-In) USB function Application IN token reception From setup stage 1 written to TRG0.EP0s RDFN? No NAK Yes Valid data in EP0i FIFO? Write data to EP0i data register (EPDR0i). No Write 1 to EP0i packet enable bit. (TRG0.EP0i PKTE = 1) NAK Yes Data transmission to host ACK Set EP0i transmission complete flag. (IFR1.EP0i TS = 1) Interrupt request Clear EP0i transmission complete flag. (IFR1.
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H8S/2456, H8S/2456R, H8S/2454 Group (3) Section 16 USB Function Module (USB) Data Stage (Control-Out) USB function Application OUT token reception 1 written to TRG0.EP0s RDFN? No NAK Yes Data reception from host ACK Set EP0o reception complete flag. (IFR1.EP0o TS = 1) Interrupt request Read data from EP0o receive data size register (EPSZ0o). OUT token reception 1 written to TRG0.EP0o RDFN? Clear EP0o reception complete flag. (IFR1.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) (4) Status Stage (Control-In) USB function Application OUT token reception 0-byte reception from host ACK Set EP0o reception complete flag (IFR1.EP0o TS = 1) End of control transfer Interrupt request Clear EP0o reception complete flag (IFR1.EP0o TS = 0) Write 1 to EP0o read complete bit (TRG0.EP0o RDFN = 1) End of control transfer Figure 16.
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H8S/2456, H8S/2456R, H8S/2454 Group (5) Section 16 USB Function Module (USB) Status Stage (Control-Out) USB function Application IN token reception Valid data in EP0i FIFO? No Interrupt request NAK Clear EP0i transfer request flag. (IFR1.EP0i TR = 0) Yes Write 1 to EP0i packet enable bit. (TRG0.EP0i PKTE = 1) 0-byte transmission to host ACK Set EP0i transmission complete flag. (IFR1.EP0i TS = 1) End of control transfer Interrupt request Clear EP0i transmission complete flag. (IFR1.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) 16.5.6 EP1 Bulk-Out Transfer USB function Application OUT token reception Space in EP1 FIFO? No NAK Yes Data reception from host Read EP1 receive data size register (EPSZ1). ACK Set EP1 FIFO full status. (IFR2.EP1 FULL = 1) Interrupt request Read data from EP1 data register (EPDR1). Write 1 to EP1 read complete bit. (TRG1.EP1 RDFN = 1) No Interrupt request Yes Clear EP1 FIFO full status. (IFR2.EP1 FULL = 0) Figure 16.
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H8S/2456, H8S/2456R, H8S/2454 Group 16.5.7 Section 16 USB Function Module (USB) EP2 Bulk-In Transfer USB function Application IN token reception Valid data in EP2 FIFO? No NAK Interrupt Set EP2 transfer request request flag. (IFR2.EP2TR = 1) Clear EP2 transfer request flag. (IFR2.EP2 TR = 0) Yes Write 1 to EP2 FIFO empty interrupt bit. (IER2.EP2 EMPTY = 1) Data transmission to host ACK Space in EP2 FIFO? Yes Set EP2 empty status. (IFR2.EP2 EMPTY = 1) Interrupt request IFR2.
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Section 16 USB Function Module (USB) (1) H8S/2456, H8S/2456R, H8S/2454 Group Dual FIFOs (EP2) EP2 has two 64-byte FIFOs, but the user can transmit data and write transmit data without being aware of this dual-FIFO configuration. However, one data write is performed for one FIFO. For example, even if both FIFOs are empty, it is not possible to perform EP2 PKTE at one time after consecutively writing 128 bytes of data. EP2 PKTE must be performed for each 64-byte write.
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H8S/2456, H8S/2456R, H8S/2454 Group 16.5.8 Section 16 USB Function Module (USB) EP3 Interrupt-In Transfer USB function Application Is there data for transmission to host? No Yes IN token reception Write data to EP3 data register (EPDR3). Valid data in EP3FIFO? No NAK Yes Write 1 to EP3 packet enable bit. (TRG1.EP3 PKTE = 1) Data transmission to host ACK Set EP3 transmission complete flag. (IFR2.EP3 TS = 1) Interrupt request Clear EP3 transmission complete flag. (IFR2.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) 16.6 Processing of USB Standard Commands and Class/ Vendor Commands 16.6.1 Processing of Commands Transmitted by Control Transfer A command transmitted from the host by control transfer may require decoding and execution of command processing on the application side. Whether command decoding is required on the application side is indicated in table 16.7 below. Table 16.
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H8S/2456, H8S/2456R, H8S/2454 Group 16.7 Stall Operations 16.7.1 Overview Section 16 USB Function Module (USB) This section describes stall operations in this module.
PAGE 1040
H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) (1) Transition from normal operation to stall (1-1) USB EPSTL 0→1 Internal status bit 0 1. 1 written to EPSTL by application (1-2) Reference Transaction request EPSTL 1 Internal status bit 0 (1-3) Stall STALL handshake EPSTL 1 Internal status bit 0→1 1. IN/OUT token received from host 2. EPSTL referenced 1. 1 set in EPSTL 2. Internal status bit set to 1 3.
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H8S/2456, H8S/2456R, H8S/2454 Group 16.7.3 Section 16 USB Function Module (USB) Automatic Stall by USB Function Module When a stall setting is made with the Set Feature command, or in the event of a USB specification violation, the USB function module automatically sets the internal status bit for the relevant endpoint without regard to the EPSTL register, and returns a stall handshake (1-1 in figure 16.20).
PAGE 1042
Section 16 USB Function Module (USB) 16.8 DMA Transfer 16.8.1 Overview H8S/2456, H8S/2456R, H8S/2454 Group DMA transfer can be performed for endpoints 1 and 2 in this module. Note that word or longword data cannot be transferred. When endpoint 1 holds at least one byte of valid receive data, a DMA request for endpoint 1 is generated. When endpoint 2 holds no valid data, a DMA request for endpoint 2 is generated.
PAGE 1043
H8S/2456, H8S/2456R, H8S/2454 Group 16.8.3 Section 16 USB Function Module (USB) DMA Transfer for Endpoints 1 and 4 When the data received at EP1 is transferred by the DMAC, the USB function module automatically performs the same processing as writing 1 to the RDFN bit in TRG1 if the currently selected FIFO becomes empty. Accordingly, in DMA transfer, do not write 1 to the RDFN bit in TRG1. If the user writes 1 to the RDFN bit in DMA transfer, correct operation cannot be guaranteed. Figure 16.
PAGE 1044
H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) 16.8.4 DMA Transfer for Endpoints 2 When the transmit data at EP2 is transferred by the DMAC, the USB function module automatically performs the same processing as writing 1 to the PKTE bit in TRG1 if the currently selected FIFO (64 bytes) becomes full. Accordingly, to transfer data of a multiple of 64 bytes, the user need not write 1 to the PKTE bit in TRG1.
PAGE 1045
H8S/2456, H8S/2456R, H8S/2454 Group 16.9 Section 16 USB Function Module (USB) Example of USB External Circuitry 1. USB Transceiver This module supports the on-chip transceiver only, not the external transceiver. 2. D+ Pull-Up Control The general output port (P20) is used for D+ pull-up control pin. The P20 pin is driven high by the PULLUP_E bit of CTLR when the USB cable VBUS is connected. Thus, USB host/hub connection notification (D+ pill-up) is enabled. 3.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) USB Vcc PULLUP_E On-chip transceiver Vcc (3.3 V) P20 VBUS*2 DrVCC (3.3 V) USD+ USD- DrVSS Vss 3.3 V Vcc *1 Vcc *1 1.5 kΩ External pull-up control circuit supporting full-speed VBUS (5 V) D+ D- GND USB connector Notes: 1. To protect this LSI from being damaged, use the IC (such as HD74LV-A Series) which can be applied voltage even when the system power is turned off. 2.
PAGE 1047
H8S/2456, H8S/2456R, H8S/2454 Group 16.10 Section 16 USB Function Module (USB) Usage Notes 16.10.1 Receiving Setup Data Note the following for EPDR0s that receives 8-byte setup data: 1. As a latest setup command must be received in high priority, the write from the USB bus takes priority over the read from the CPU. If the next setup command reception is started while the CPU is reading data after the data is received, the read from the CPU is forcibly terminated.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) 16.10.4 Assigning Interrupt Sources to EP0 The EP0-related interrupt sources indicated by the interrupt source bits (bits 0 to 3) in IFR0 must be assigned to the same interrupt signal with ISR0. The other interrupt sources have no limitations. 16.10.5 Clearing the FIFO When DMA Transfer is Enabled EPDR1 cannot be cleared when DMA transfer for endpoint 1 is enabled (EP1DMAE in DMAR = 1).
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H8S/2456, H8S/2456R, H8S/2454 Group Section 16 USB Function Module (USB) 16.10.7 Module Stop Function Setting Operation of the USB function module can be disabled or enabled using the module stop control register. The initial setting is for operation of the USB function module to be halted. Register access is enabled by clearing the module stop state. After clearing the module stop state, set the register after executing a 26-state dummy read.
PAGE 1050
Section 16 USB Function Module (USB) Page 1020 of 1408 H8S/2456, H8S/2456R, H8S/2454 Group R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 17 I2C Bus Interface 2 (IIC2) Section 17 I2C Bus Interface 2 (IIC2) This LSI has a four-channel I2C bus interface. The I2C bus interface conforms to and provides a subset of the NXP I2C bus (inter-IC bus) interface functions (Rev. 0.3) for standard-mode and fast-mode. The register configuration that controls the I2C bus differs partly from the NXP configuration, however. Figure 17.1 shows a block diagram of the I2C bus interface 2. Figure 17.
PAGE 1052
Section 17 I2C Bus Interface 2 (IIC2) H8S/2456, H8S/2456R, H8S/2454 Group Transfer clock generation circuit Transmission/ reception control circuit Output control SCL ICCRA ICCRB ICMR Internal data bus Noise canceler ICDRT Output control SDA ICDRS SAR Address comparator Noise canceler ICDRR Bus state decision circuit Arbitration decision circuit ICSR ICEIR Interrupt generator [Legend] ICCRA: ICCRB: ICMR: ICSR: ICIER: ICDRT: ICDRR: ICDRS: SAR: Interrupt request 2 I C bus control register
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Section 17 I2C Bus Interface 2 (IIC2) H8S/2456, H8S/2456R, H8S/2454 Group Vcc SCL in Vcc SCL SCL SDA SDA SCL out SDA in SCL in SCL SDA (Master) SCL SDA SDA out SCL in SCL out SCL out SDA in SDA in SDA out SDA out (Slave 1) (Slave 2) Figure 17.2 External Circuit Connections of I/O Pins 17.2 Input/Output Pins Table 17.1 shows the pin configuration of the I2C bus interface 2. Table 17.
PAGE 1054
Section 17 I2C Bus Interface 2 (IIC2) 17.3 H8S/2456, H8S/2456R, H8S/2454 Group Register Descriptions The I2C bus interface has the following registers.
PAGE 1055
H8S/2456, H8S/2456R, H8S/2454 Group Section 17 I2C Bus Interface 2 (IIC2) Channel 2 • • • • • • • • • I2C bus control register A_2 (ICCRA_2) I2C bus control register B_2 (ICCRB_2) I2C bus mode register_2 (ICMR_2) I2C bus interrupt enable register_2 (ICIER_2) I2C bus status register_2 (ICSR_2) Slave address register_2 (SAR_2) I2C bus transmit data register_2 (ICDRT_2) I2C bus receive data register_2 (ICDRR_2) I2C bus shift register_2 (ICDRS_2) Channel 3 • • • • • • • • • I2C bus control register A_3 (IC
PAGE 1056
Section 17 I2C Bus Interface 2 (IIC2) 17.3.1 H8S/2456, H8S/2456R, H8S/2454 Group I2C Bus Control Register A (ICCRA) ICCRA is an 8-bit readable/writable register that enables or disables the I2C bus interface, controls transmission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode. Bit Bit Name Initial Value R/W Description 7 ICE 0 R/W I2C Bus Interface Enable 0: Disables SCL/SDA outputs. (Inputs to SCL/SDA are available.
PAGE 1057
Section 17 I2C Bus Interface 2 (IIC2) H8S/2456, H8S/2456R, H8S/2454 Group Table 17.
PAGE 1058
Section 17 I2C Bus Interface 2 (IIC2) 17.3.2 H8S/2456, H8S/2456R, H8S/2454 Group I2C Bus Control Register B (ICCRB) ICCRB is an 8-bit readable/writable register that issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls reset in I2C control. Bit Bit Name Initial Value R/W Description 7 BBSY 0 R/W Bus Busy 2 This bit enables to confirm whether the I C bus is occupied or released and to issue start and stop conditions in master mode.
PAGE 1059
Section 17 I2C Bus Interface 2 (IIC2) H8S/2456, H8S/2456R, H8S/2454 Group Bit Bit Name Initial Value R/W Description 1 IICRST 0 R/W IIC Control Part Reset 2 This bit resets control parts except for I C registers. If this bit is set to 1 when hang-up is occurred because of communication failure during 2 2 I C operation, I C control part can be reset without setting ports and initializing registers. 0 ⎯ 1 ⎯ Reserved This bit is always read as 1. 17.3.
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Section 17 I2C Bus Interface 2 (IIC2) H8S/2456, H8S/2456R, H8S/2454 Group Bit Bit Name Initial Value R/W Description 2 BC2 0 R/W Bit Counter 2 to 0 1 BC1 0 R/W 0 BC0 0 R/W These bits specify the number of bits to be transferred next. When read, the remaining number of transfer bits is indicated. The data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames.
PAGE 1061
Section 17 I2C Bus Interface 2 (IIC2) H8S/2456, H8S/2456R, H8S/2454 Group 17.3.4 I2C Bus Interrupt Enable Register (ICIER) ICIER is an 8-bit readable/writable register that enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be received.
PAGE 1062
Section 17 I2C Bus Interface 2 (IIC2) H8S/2456, H8S/2456R, H8S/2454 Group Bit Bit Name Initial Value R/W Description 4 NAKIE 0 R/W NACK Receive Interrupt Enable This bit enables or disables the NACK receive interrupt request (NAKI) when the NACKF and AL bits in ICSR are set to 1. NAKI can be canceled by clearing the NACKF, AL, or NAKIE bit to 0. 0: NACK receive interrupt request (NAKI) is disabled. 1: NACK receive interrupt request (NAKI) is enabled.
PAGE 1063
Section 17 I2C Bus Interface 2 (IIC2) H8S/2456, H8S/2456R, H8S/2454 Group 17.3.5 I2C Bus Status Register (ICSR) ICSR is an 8-bit readable/writable register that performs confirmation of interrupt request flags and status. Bit Bit Name Initial Value R/W 7 TDRE 0 R/W Description Transmit Data Register Empty [Setting condition] • When data is transferred from ICDRT to ICDRS and ICDRT becomes empty. • When TRS has been set. • When a start condition (including retransmission) has been issued.
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Section 17 I2C Bus Interface 2 (IIC2) H8S/2456, H8S/2456R, H8S/2454 Group Bit Bit Name Initial Value R/W Description 4 NACKF 0 R/W No Acknowledge Detection Flag [Setting condition] • When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1. [Clearing condition] • 3 STOP 0 R/W When 0 is written in NACKF after reading NACKF = 1. Stop Condition Detection Flag [Setting condition] • When a stop condition is detected after frame transfer.
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Section 17 I2C Bus Interface 2 (IIC2) H8S/2456, H8S/2456R, H8S/2454 Group Bit Bit Name Initial Value R/W Description 1 AAS 0 R/W Slave Address Recognition Flag In slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR. [Setting condition] • When the slave address is detected in slave receive mode. • When the general call address is detected in slave receive mode.
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Section 17 I2C Bus Interface 2 (IIC2) 17.3.7 H8S/2456, H8S/2456R, H8S/2454 Group I2C Bus Transmit Data Register (ICDRT) ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the I2C bus shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible.
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Section 17 I2C Bus Interface 2 (IIC2) H8S/2456, H8S/2456R, H8S/2454 Group 17.4 Operation 17.4.1 I2C Bus Format Figure 17.3 shows the I2C bus formats. Figure 17.4 shows the I2C bus timing. The first frame following a start condition always consists of 8 bits.
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Section 17 I2C Bus Interface 2 (IIC2) H8S/2456, H8S/2456R, H8S/2454 Group Legend: S: Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. A: Acknowledge. The receiving device drives SDA to low. DATA: Transferred data P: 17.4.2 Stop condition.
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Section 17 I2C Bus Interface 2 (IIC2) H8S/2456, H8S/2456R, H8S/2454 Group SCL (master output) 1 2 3 4 5 6 SDA (master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 7 8 Bit 1 Slave address 9 1 Bit 0 Bit 7 2 Bit 6 R/W SDA (slave output) A TDRE TEND Address + R/W ICDRT ICDRS Data 1 Address + R/W User [2] Instruction of start processing condition issuance Data 2 Data 1 [4] Write data to ICDRT (second byte). [3] Write data to ICDRT (first byte).
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Section 17 I2C Bus Interface 2 (IIC2) 17.4.3 H8S/2456, H8S/2456R, H8S/2454 Group Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCRA to 0 to switch from master transmit mode to master receive mode. Then, clear the TDRE bit to 0. 2.
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Section 17 I2C Bus Interface 2 (IIC2) H8S/2456, H8S/2456R, H8S/2454 Group Master transmit mode SCL (master output) Master receive mode 9 1 2 3 4 5 6 7 8 SDA (master output) SDA (slave output) 9 1 A A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS RDRF ICDRS Data 1 ICDRR User processing Data 1 [3] Read ICDRR [1] Clear TDRE after clearing TEND and TRS [2] Read ICDRR (dummy read) Figure 17.7 Master Receive Mode Operation Timing 1 R01UH0309EJ0500 Rev. 5.
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Section 17 I2C Bus Interface 2 (IIC2) SCL (master output) 9 SDA (master output) A SDA (slave output) 1 H8S/2456, H8S/2456R, H8S/2454 Group 2 3 4 5 6 7 8 9 A/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RDRF RCVD ICDRS Data n Data n-1 ICDRR User processing Data n Data n-1 [5] Read ICDRR after setting RCVD. [6] Issue stop condition [7] Read ICDRR and clear RCVD [8] Set slave receive mode Figure 17.
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H8S/2456, H8S/2456R, H8S/2454 Group 17.4.4 Section 17 I2C Bus Interface 2 (IIC2) Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. 1. Set the ICE bit in ICCRA to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCRA to 1.
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Section 17 I2C Bus Interface 2 (IIC2) Slave receive mode SCL (master output) H8S/2456, H8S/2456R, H8S/2454 Group Slave transmit mode 9 1 2 3 4 5 6 7 8 SDA (master output) 9 1 A SCL (slave output) SDA (slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 7 Bit 0 TDRE TEND TRS ICDRT ICDRS Data 1 Data 2 Data 1 Data 3 Data 2 ICDRR User processing [2] Write data to ICDRT (data 1). [2] Write data to ICDRT (data 2). [2] Write data to ICDRT (data 3). Figure 17.
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Section 17 I2C Bus Interface 2 (IIC2) H8S/2456, H8S/2456R, H8S/2454 Group Slave receive mode Slave transmit mode SCL (master output) 9 SDA (master output) A 1 2 3 4 5 6 7 8 9 A/A SCL (slave output) SDA (slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TDRE TEND TRS ICDRT ICDRS Data n ICDRR User processing [3] Clear TEND [4] Read ICDRR (dummy read) after clearing TRS [5] Clear TDRE Figure 17.10 Slave Transmit Mode Operation Timing 2 R01UH0309EJ0500 Rev. 5.
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Section 17 I2C Bus Interface 2 (IIC2) 17.4.5 H8S/2456, H8S/2456R, H8S/2454 Group Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The reception procedure and operations in slave receive mode are described below. 1. Set the ICE bit in ICCRA to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCRA to 1.
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Section 17 I2C Bus Interface 2 (IIC2) H8S/2456, H8S/2456R, H8S/2454 Group SCL (master output) 9 SDA (master output) 1 2 3 4 5 6 7 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 1 Bit 7 SCL (slave output) SDA (slave output) A A RDRF ICDRS Data 1 Data 2 ICDRR User processing Data 1 [7] Read ICDRR. [4] Read ICDRR (dummy read). Figure 17.
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Section 17 I2C Bus Interface 2 (IIC2) 17.4.6 H8S/2456, H8S/2456R, H8S/2454 Group Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 17.13 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree.
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Section 17 I2C Bus Interface 2 (IIC2) H8S/2456, H8S/2456R, H8S/2454 Group Start Initialize Read BBSY in ICCRB [1] Test the status of the SCL and SDA lines. [2] Select master transmit mode. [3] Start condition issuance. [4] Select transmit data for the first byte (slave address + R/W). [5] Wait for 1 byte to be transmitted. [6] Test the acknowledge bit, transferred from the specified slave device. [7] Set transmit data for the second and subsequent data (except for the final byte).
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Section 17 I2C Bus Interface 2 (IIC2) H8S/2456, H8S/2456R, H8S/2454 Group Mater receive mode [1] Clear TEND, select master receive mode, and then clear TDRE.* [2] Set acknowledge to the transmitting device.* [3] Dummy read ICDDR.* [4] Wait for 1 byte to be received. [5] Check if the (last receive - 1). [6] Read the receive data. [7] Set acknowledge of the final byte. Disable continuous receive (RCVD = 1). [8] Read receive data of (final byte - 1).
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Section 17 I2C Bus Interface 2 (IIC2) H8S/2456, H8S/2456R, H8S/2454 Group [1] Clear the flag AAS. Slave transmit mode Clear AAS in ICSR [1] Write transmit data in ICDRT [2] [3] Wait for ICDRT empty. [4] Set the last byte of the transmit data. Read TDRE in ICSR No [5] Wait the transmission end of the last byte. [3] TDRE=1 ? Yes No [6] Clear the flag TEND. [7] Set slave receive mode. End of transmission? Yes [2] Set transmit data for ICDRT (except for the last data).
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Section 17 I2C Bus Interface 2 (IIC2) H8S/2456, H8S/2456R, H8S/2454 Group Slave receive mode Read RDRF in ICSR No RDRF=1 ? Yes Read AAS in ICSR No Set RIE = 0 in ICIER AAS=1 ? [2] Clear the flag AAS. Yes Clear AAS in ICSR [12] Read STOP in ICSR No [1] [1] Determination of slave address* Use receive-data-full interrupts to determine whether the slave address matches. • If the slave address did match (AAS = 1), execute steps [2] to [11].
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Section 17 I2C Bus Interface 2 (IIC2) H8S/2456, H8S/2456R, H8S/2454 Group 17.5 Interrupt Request There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK detection, STOP recognition, and arbitration lost. Table 17.3 shows the contents of each interrupt request. Table 17.
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Section 17 I2C Bus Interface 2 (IIC2) 17.6 H8S/2456, H8S/2456R, H8S/2454 Group Bit Synchronous Circuit In master mode, • • When SCL is driven to low by the slave device When the rising speed of SCL is lower by the load of the SCL line (load capacitance or pullup resistance) This module has a possibility that high level period may be short in the two states described above. Therefore it monitors SCL and communicates by bit with synchronization. Figure 17.
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H8S/2456, H8S/2456R, H8S/2454 Group 17.7 Section 17 I2C Bus Interface 2 (IIC2) Usage Notes 1. Issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed. Check SCLO in the I2C control register B (IICRB) to confirm the fall of the ninth clock. When the start/stop conditions are issued (retransmitted) at the specific timing under the following condition (i) or (ii), such conditions may not be output successfully. This does not occur in other cases.
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Section 17 I2C Bus Interface 2 (IIC2) H8S/2456, H8S/2456R, H8S/2454 Group ⎯ Write 0 to BBSY and SCP in ICCRB to issue the stop condition when SDA = low in master transmission or master reception mode and this module is the only module which pulls SCL low. BBSY is cleared to 0 when the stop condition (SCL = high and SDA rising) is output. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 17 I2C Bus Interface 2 (IIC2) 8. Notes on Changing from Master Transmit Mode to Master Receive Mode If TRS is cleared to 0 before the falling edge of the 9th clock in master transmit mode when master transmit mode is changed to master receive mode, this module outputs the receive clock in synchronization with the internal clock whether ICDRR is read (dummy read) or not.
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Section 17 I2C Bus Interface 2 (IIC2) Page 1058 of 1408 H8S/2456, H8S/2456R, H8S/2454 Group R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 18 A/D Converter Section 18 A/D Converter This LSI includes two units (units 0 and 1) of successive approximation type 10-bit A/D converter. In the H8S/2456 group and H8S/2456R group, the A/D converter units 0 and 1 allow up to eight analog input channels to be selected. In the H8S/2454 group, unit 0 allows up to eight analog input channels to be selected while unit 1 allows up to two channels. Figures 18.1 and 18.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 18 A/D Converter Internal data bus AVSS Bus interface ADCR_0 ADCSR_0 ADDRH_0 ADDRG_0 ADDRF_0 ADDRE_0 ADDRD_0 ADDRC_0 ADDRB_0 10-bit A/D Vref ADDRA_0 AVCC Successive approximation register Module data bus AN0 + AN1 AN2 Multiplexer – AN3 AN4 AN5 AN6 Comparator Control circuit Sample-andhold circuit AN7 ADI0 interrupt signal ADTRG0-A ADTRG0-B [Legend] ADCR_0: ADCSR_0: ADDRA_0: ADDRB_0: ADDRC_0: Conversion start trigger from TPU (units 0,
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H8S/2456, H8S/2456R, H8S/2454 Group Section 18 A/D Converter Internal data bus AVSS Bus interface ADCR_1 ADCSR_1 ADDRH_1 ADDRG_1 ADDRF_1 ADDRE_1 ADDRD_1 ADDRC_1 ADDRB_1 10-bit A/D Vref ADDRA_1 AVCC Successive approximation register Module data bus AN8* + AN9* – Multiplexer AN10* AN11* AN12 AN13 Comparator Control circuit Sample-andhold circuit AN14* AN15* ADI1 interrupt signal ADTRG1 [Legend] ADCR_1: ADCSR_1: ADDRA_1: ADDRB_1: ADDRC_1: Conversion start trigger from TPU (units 0,
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H8S/2456, H8S/2456R, H8S/2454 Group Section 18 A/D Converter 18.2 Input/Output Pins Tables 18.1 and 18.2 show the pin configuration of the A/D converter. Table 18.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 18 A/D Converter Table 18.2 Pin Configuration (H8S/2454 Group) Unit Abbr.
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Section 18 A/D Converter 18.3 H8S/2456, H8S/2456R, H8S/2454 Group Register Descriptions The A/D converter has the following registers.
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H8S/2456, H8S/2456R, H8S/2454 Group 18.3.1 Section 18 A/D Converter A/D Data Registers A to H (ADDRA to ADDRH) There are eight 16-bit read-only ADDR registers, ADDRA to ADDRH, used to store the results of A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown in tables 18.3 and 18.4. The converted 10-bit data is stored in bits 15 to 6. The lower 6-bit data is always read as 0. The data bus between the CPU and the A/D converter has a 16-bit width.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 18 A/D Converter Table 18.
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H8S/2456, H8S/2456R, H8S/2454 Group 18.3.2 Section 18 A/D Converter A/D Control/Status Register for Unit 0 (ADCSR_0) ADCSR_0 controls A/D conversion operations. Bit Bit Name Initial Value 7 ADF 0 R/W Description R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 18 A/D Converter Bit Bit Name Initial Value R/W Description 3 2 1 0 CH3 CH2 CH1 CH0 0 0 0 0 R/W R/W R/W R/W Channel Select 3 to 0 Selects analog input together with bits SCANE and SCANS in ADCR.
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H8S/2456, H8S/2456R, H8S/2454 Group 18.3.3 Section 18 A/D Converter A/D Control/Status Register for Unit 1 (ADCSR_1) ADCSR_1 controls A/D conversion operations. Bit Bit Name Initial Value 7 ADF 0 R/W Description R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 18 A/D Converter • H8S/2456 Group and H8S/2456R Group Bit Bit Name Initial Value R/W Description 3 2 1 0 CH3 CH2 CH1 CH0 0 0 0 0 R/W R/W R/W R/W Channel Select 3 to 0 Selects analog input together with bits SCANE and SCANS in ADCR.
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H8S/2456, H8S/2456R, H8S/2454 Group • Section 18 A/D Converter H8S/2454 Group Bit Bit Name Initial Value R/W Description 3 2 1 0 CH3 CH2 CH1 CH0 0 0 0 0 R/W R/W R/W R/W Channel Select 3 to 0 Selects analog input together with bits SCANE and SCANS in ADCR.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 18 A/D Converter 18.3.4 A/D Control Register (ADCR_0) Unit 0 ADCR enables A/D conversion to be started by an external trigger input. Bit Bit Name Initial Value R/W Description 7 TRGS1 0 R/W Timer Trigger Select 1 and 0 and Extended Trigger Select 6 TRGS0 0 R/W 0 EXTRGS 0 R/W These bits enable or disable the start of A/D conversion by a trigger signal.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 18 A/D Converter Bit Bit Name Initial Value R/W Description 5 SCANE 0 R/W Scan Mode 4 SCANS 0 R/W These bits select the A/D conversion operating mode. 0x: Single mode 10: Scan mode. A/D conversion is performed continuously for channels 1 to 4. 11: Scan mode. A/D conversion is performed continuously for channels 1 to 8.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 18 A/D Converter 18.3.5 A/D Control Register (ADCR_1) Unit 1 ADCR enables A/D conversion to be started by an external trigger input. Bit Bit Name Initial Value R/W Description 7 TRGS1 0 R/W Timer Trigger Select 1 and 0 and Extended Trigger Select 6 TRGS0 0 R/W 0 EXTRGS 0 R/W These bits enable or disable the start of A/D conversion by a trigger signal.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 18 A/D Converter Bit Bit Name Initial Value R/W Description 3 CKS1 0 R/W Clock Select 1 and 0 2 CKS0 0 R/W These bits select the A/D conversion clock (ADCLK) and specify the A/D conversion time in combination with the EXCKS bit. First select the A/D conversion time while ADST = 0 in ADCSR and then set the mode of A/D conversion. Before entering software standby mode or module stop state, set these bits to B'11.
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Section 18 A/D Converter 18.4 H8S/2456, H8S/2456R, H8S/2454 Group Operation The A/D converter has two operating modes: single mode and scan mode. First select the clock for A/D conversion (ADCLK). When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the ADST bit in ADCSR to 0. The ADST bit can be set to 1 at the same time as the operating mode or analog input channel is changed. 18.4.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 18 A/D Converter Set* ADIE Set* ADST Set* A/D conversion start Clear* Clear* ADF Channel 0 (AN0) operation state Channel 1 (AN1) operation state Waiting for conversion Waiting for conversion A/D conversion 1 Channel 2 (AN2) operation state Waiting for conversion Channel 3 (AN3) operation state Waiting for conversion Waiting for conversion A/D conversion 2 Waiting for conversion ADDRA Reading A/D conversion result A/D conversion result 1 ADDRB Re
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Section 18 A/D Converter 18.4.2 H8S/2456, H8S/2456R, H8S/2454 Group Scan Mode In scan mode, A/D conversion is to be performed sequentially on the analog inputs of the specified channels up to four or eight* channels. Two types of scan mode are provided, that is, continuous scan mode where A/D conversion is repeatedly performed and one-cycle scan mode where A/D conversion is performed for the specified channels for one cycle. (1) Continuous Scan Mode 1.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 18 A/D Converter A/D conversion consecutive execution Clear*1 Set*1 ADST Clear*1 ADF Channel 0 (AN0) operation state Waiting for conversion A/D conversion 1 Channel 1 (AN1) operation state Waiting for conversion Channel 2 (AN2) operation state Waiting for conversion Channel 3 (AN3) operation state Waiting for conversion A/D conversion time Waiting for conversion A/D conversion 2 A/D conversion 4 Waiting for conversion A/D conversion 3 Waiting for
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Section 18 A/D Converter (2) H8S/2456, H8S/2456R, H8S/2454 Group One-Cycle Scan Mode 1. Set the ADSTCLR bit in ADCR to 1. 2. When the ADST bit in ADCSR is set to 1 by software, TPU, TMR, or an external trigger input, A/D conversion starts on the first channel in the specified channel group. Consecutive A/D conversion on a maximum of four channels (SCANE and SCANS = B'10) or on a maximum of eight channels (SCANE and SCANS = B'11) can be selected.
PAGE 1111
H8S/2456, H8S/2456R, H8S/2454 Group Section 18 A/D Converter A/D conversion one-cycle execution Set * ADST Clear* ADF A/D conversion time Channel 4 (AN4) Waiting for conversion operation state Channel5 (AN5) operation state Channel 6 (AN6) operation state Waiting for conversion A/D conversion 1 Waiting for conversion Waiting for conversion A/D conversion 2 Waiting for conversion Waiting for conversion A/D conversion 3 Channel 7 (AN7) operation state Waiting for conversion Transfer ADDRE A/D c
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H8S/2456, H8S/2456R, H8S/2454 Group Section 18 A/D Converter 18.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) passes after the ADST bit in ADCSR is set to 1, then starts A/D conversion. Figure 18.6 shows the A/D conversion timing. Tables 18.5 and 18.6 show the A/D conversion time. As shown in figure 18.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 18 A/D Converter Table 18.5 A/D Conversion Characteristics (EXCKS = 0) CKS1 = 0 CKS1 = 1 CKS = 1 CKS = 0 CKS = 1 Item Symbol Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. A/D conversion start tD 4 ⎯ 10 4 ⎯ 8 3 ⎯ 7 Input sampling time tSPL ⎯ 156 ⎯ ⎯ 78 ⎯ ⎯ 39 ⎯ A/D conversion time tCONV 262 ⎯ 268 134 ⎯ 138 69 ⎯ 73 delay time Note: Values in the table are the number of states. Table 18.
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Section 18 A/D Converter 18.4.4 H8S/2456, H8S/2456R, H8S/2454 Group External Trigger Input Timing A/D conversion can be externally triggered. For unit 0, an external trigger is input from the ADTRG0 pin when the TRGS1, TRGS0, and EXTRGS bits are set to B'110 or B'001 in ADCR_0. For unit 1, an external trigger is input from the ADTRG1 pin when the TRGS1, TRGS0, and EXTRGS bits are set to B'110 in ADCR_1.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 18 A/D Converter φ ADTRG0 Internal trigger signal ADST A/D conversion Figure 18.8 External Trigger Input Timing when Multiple Units Start Simultaneously (TRSG1, TRGS0, and EXTRGS = B'111) 18.5 Interrupt Source The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. Setting the ADIE bit to 1 when the ADF bit in ADCSR is set to 1 after A/D conversion is completed enables ADI interrupt requests.
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Section 18 A/D Converter 18.6 H8S/2456, H8S/2456R, H8S/2454 Group A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes. • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 18.9).
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H8S/2456, H8S/2456R, H8S/2454 Group Section 18 A/D Converter Digital output Ideal A/D conversion characteristic 111 110 101 100 011 010 Quantization error 001 000 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 18.9 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Offset error FS Analog input voltage Figure 18.
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Section 18 A/D Converter 18.7 Usage Notes 18.7.1 Module Stop Function Setting H8S/2456, H8S/2456R, H8S/2454 Group Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing the module stop state.
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H8S/2456, H8S/2456R, H8S/2454 Group 18.7.4 Section 18 A/D Converter Permissible Signal Source Impedance This LSI's analog input is designed so that the conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less.
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Section 18 A/D Converter 18.7.6 H8S/2456, H8S/2456R, H8S/2454 Group Setting Range of Analog Power Supply and Other Pins If the conditions shown below are not met, the reliability of the LSI may be adversely affected. • Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss ≤ VAN ≤ Vref. • Relation between AVss and Vss, and AVcc and Vcc As the relationship between AVss and Vss, set AVss = Vss.
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H8S/2456, H8S/2456R, H8S/2454 Group 18.7.8 Section 18 A/D Converter Notes on Noise Countermeasures A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN15*) should be connected between AVcc and AVss as shown in figure 18.12. Also, the bypass capacitors connected to AVcc and the filter capacitor connected to the AN0 to AN11 pins must be connected to AVss.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 18 A/D Converter 18.7.9 Concurrent Operation of Two A/D Converters When operating two A/D converters concurrently, if conversion by the two converters starts at different times, the accuracy of conversion may be affected by crosstalk between the two converters. When converter Y starts A/D conversion during the period indicated by TX-Y in figure 18.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 18 A/D Converter 18.7.10 Notes on Start of A/D Conversion by Conversion Start Trigger from TPU (Units 0 and 1) When A/D conversion starts by a conversion start trigger from the TPU, the register settings of the TPU and A/D converters must be checked so that A/D conversion does not start at unintended timing.
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Section 18 A/D Converter Page 1094 of 1408 H8S/2456, H8S/2456R, H8S/2454 Group R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 19 D/A Converter Section 19 D/A Converter 19.1 Features D/A converter features are listed below. • • • • • • 8-bit resolution Output channels: Two channels Maximum conversion time of 10 µs (with 20 pF load) Output voltage of 0 V to Vref D/A output hold function in software standby mode Module stop state can be set. R01UH0309EJ0500 Rev. 5.
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Module data bus Bus interface H8S/2456, H8S/2456R, H8S/2454 Group Section 19 D/A Converter Internal data bus DA2 D/A DACR23 8-bit DA3 DADR3 AVcc DADR2 Vref AVss Control circuit [Legend] DADR2: D/A data register 2 DADR3: D/A data register 3 DACR23: D/A control register 23 Figure 19.1 Block Diagram of D/A Converter Page 1096 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group 19.2 Section 19 D/A Converter Input/Output Pins Table 19.1 shows the pin configuration of the D/A converter. Table 19.1 Pin Configuration Pin Name Symbol I/O Function Analog power pin Analog ground pin AVCC Input Analog power AVSS Input Analog ground Reference voltage pin Vref Input Reference voltage of D/A converter Analog output pin 2 DA2 Output Channel 2 analog output Analog output pin 3 DA3 Output Channel 3 analog output 19.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 19 D/A Converter 19.3.2 D/A Control Register 23 (DACR23) DACR23 controls the operation of channels 2 and 3 in the D/A converter. Bit Bit Name Initial Value R/W Description 7 DAOE3 0 R/W D/A Output Enable 3 Controls D/A conversion and analog output. 0: Channel 3 analog output (DA3) is disabled. 1: Channel 3 D/A conversion is enabled; channel 3 analog output (DA3) is enabled.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 19 D/A Converter Table 19.2 Control of D/A Conversion Bit 5 DAE Bit 7 Bit 6 DAOE3 DAOE2 Description 0 0 0 D/A conversion disabled 1 Channel 2 D/A conversion enabled, and channel 3 D/A conversion disabled. Channel 2 analog output (DA2) enabled, and channel 3 analog output (DA3) disabled. 1 0 Channel 2 D/A conversion disabled, and channel 3 D/A conversion enabled. Channel 2 analog output (DA2) disabled, channel 3 analog output (DA3) enabled.
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Section 19 D/A Converter 19.4 H8S/2456, H8S/2456R, H8S/2454 Group Operation The D/A converter includes D/A conversion circuits for two channels, each of which can operate independently. When DAOE bit in DACR23 is set to 1, D/A conversion is enabled and the conversion result is output. The following shows an example of D/A conversion on channel 2. Figure 19.2 shows the timing of this operation. 1. Write the conversion data to DADR2. 2. Set the DAOE2 bit in DACR23 to 1. D/A conversion is started.
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H8S/2456, H8S/2456R, H8S/2454 Group DADR2 write cycle Section 19 D/A Converter DADR2 write cycle DACR23 write cycle DACR23 write cycle φ Address DADR2 Conversion data 1 Conversion data 2 DAOE2 DA2 Conversion result 2 Conversion result 1 High-impedance state tDCONV tDCONV Legend: tDCONV: D/A conversion time Figure 19.2 Example of D/A Converter Operation R01UH0309EJ0500 Rev. 5.
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Section 19 D/A Converter 19.5 Usage Notes 19.5.1 Module Stop Function Setting H8S/2456, H8S/2456R, H8S/2454 Group D/A converter operation can be disabled or enabled using the module stop control register. The initial setting is for the D/A converter to be halted. Register access is enabled by clearing the module stop state. For details, see section 24, Power-Down Modes. 19.5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 20 Synchronous Serial Communication Unit (SSU) Section 20 Synchronous Serial Communication Unit (SSU) This LSI has one channel of synchronous serial communication unit (SSU). The SSU has master mode in which this LSI outputs clocks as a master device for synchronous serial communication and slave mode in which clocks are input from an external device for synchronous serial communication.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 20 Synchronous Serial Communication Unit (SSU) Module data bus SSCRH Bus interface Figure 20.1 shows a block diagram of the SSU.
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H8S/2456, H8S/2456R, H8S/2454 Group 20.2 Section 20 Synchronous Serial Communication Unit (SSU) Input/Output Pins Table 20.1 shows the SSU pin configuration. Table 20.1 Pin Configuration Channel Symbol I/O Function 0 SSCK0 I/O SSU clock input/output SSI0 I/O SSU data input/output SSO0 I/O SSU data input/output SCS0 I/O SSU chip select input/output Note: * Because channel numbers are omitted in later descriptions, these are shown SSCK, SSI, SSO, and SCS. R01UH0309EJ0500 Rev. 5.
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Section 20 Synchronous Serial Communication Unit (SSU) 20.3 H8S/2456, H8S/2456R, H8S/2454 Group Register Descriptions The SSU has the following registers.
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H8S/2456, H8S/2456R, H8S/2454 Group 20.3.1 Section 20 Synchronous Serial Communication Unit (SSU) SS Control Register H (SSCRH) SSCRH specifies master/slave device selection, bidirectional mode enable, SSO pin output value selection, SSCK pin selection, and SCS pin selection. Bit Bit Name Initial Value R/W Description 7 MSS 0 R/W Master/Slave Device Select Selects that this module is used in master mode or slave mode. When master mode is selected, transfer clocks are output from the SSCK pin.
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Section 20 Synchronous Serial Communication Unit (SSU) H8S/2456, H8S/2456R, H8S/2454 Group Bit Bit Name Initial Value R/W Description 4 SOL 0 R/W Serial Data Output Value Select The serial data output retains its level of the last bit after completion of transmission. The output level before or after transmission can be specified by setting this bit. When specifying the output level, use the MOV instruction after clearing the SOLP bit to 0.
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H8S/2456, H8S/2456R, H8S/2454 Group 20.3.2 Section 20 Synchronous Serial Communication Unit (SSU) SS Control Register L (SSCRL) SSCRL selects operating mode, software reset, and transmit/receive data length. Bit Bit Name Initial Value R/W Description 7 ⎯ 0 R/W Reserved This bit is always read as 0. The write value should always be 0. 6 SSUMS 0 R/W Selects transfer mode from SSU mode and clock synchronous mode.
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Section 20 Synchronous Serial Communication Unit (SSU) 20.3.3 H8S/2456, H8S/2456R, H8S/2454 Group SS Mode Register (SSMR) SSMR selects the MSB first/LSB first, clock polarity, clock phase, and clock rate of synchronous serial communication. Bit Bit Name Initial Value R/W Description 7 MLS 0 R/W 6 CPOS 0 R/W MSB First/LSB First Select Selects that the serial data is transmitted in MSB first or LSB first. 0: LSB first 1: MSB first Clock Polarity Select Selects the SSCK clock polarity.
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H8S/2456, H8S/2456R, H8S/2454 Group 20.3.4 Section 20 Synchronous Serial Communication Unit (SSU) SS Enable Register (SSER) SSER performs transfer/receive control of synchronous serial communication and setting of interrupt enable. Bit Bit Name Initial Value R/W Description 7 TE 0 R/W Transmit Enable 6 RE 0 R/W Receive Enable When this bit is set to 1, transmission is enabled. When this bit is set to 1, reception is enabled. 5, 4 ⎯ All 0 R/W Reserved These bits are always read as 0.
PAGE 1142
Section 20 Synchronous Serial Communication Unit (SSU) 20.3.5 H8S/2456, H8S/2456R, H8S/2454 Group SS Status Register (SSSR) SSSR is a status flag register for interrupts. Bit Bit Name Initial Value R/W Description 7 ⎯ 0 ⎯ 6 ORER 0 R/W Reserved This bit is always read as 0. The write value should always be 0. Overrun Error If the next data is received while RDRF = 1, an overrun error occurs, indicating abnormal termination.
PAGE 1143
H8S/2456, H8S/2456R, H8S/2454 Group Section 20 Synchronous Serial Communication Unit (SSU) Bit Bit Name Initial Value R/W Description 2 TDRE 1 R/W 1 RDRF 0 R/W 0 CE 0 R/W Transmit Data Empty Indicates whether or not SSTDR contains transmit data. [Setting conditions] • When the TE bit in SSER is 0 • When data is transferred from SSTDR to SSTRSR and SSTDR is ready to be written to.
PAGE 1144
Section 20 Synchronous Serial Communication Unit (SSU) 20.3.6 H8S/2456, H8S/2456R, H8S/2454 Group SS Control Register 2 (SSCR2) SSCR2 is a register that enables/disables the open-drain outputs of the SSO, SSI, SSCK, and SCS pins, selects the assert timing of the SCS pin, data output timing of the SSO pin, and set timing of the TEND bit.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 20 Synchronous Serial Communication Unit (SSU) Bit Bit Name Initial Value R/W Description 3 SCSATS 0 R/W Selects the assertion timing of the SCS pin (valid in SSU and master mode). 0: Min. values of tLEAD and tLAG are 1/2 × tSUcyc 1: Min.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 20 Synchronous Serial Communication Unit (SSU) 20.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3) SSTDR is an 8-bit register that stores transmit data. When 8-bit data length is selected by bits DATS1 and DATS0 in SSCRL, SSTDR0 is valid. When 16-bit data length is selected, SSTDR0 and SSTDR1 are valid. When 24-bit data length is selected, SSTDR0, SSTDR1, and SSTDR2 are valid. When 32-bit data length is selected, SSTDR0 to SSTDR3 are valid.
PAGE 1147
H8S/2456, H8S/2456R, H8S/2454 Group 20.3.8 Section 20 Synchronous Serial Communication Unit (SSU) SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3) SSRDR is an 8-bit register that stores receive data. When 8-bit data length is selected by bits DATS1 and DATS0 in SSCRL, SSRDR0 is valid. When 16-bit data length is selected, SSRDR0 and SSRDR1 are valid. When 24-bit data length is selected, SSRDR0, SSRDR1, and SSRDR2 are valid. When 32-bit data length is selected, SSRDR0 to SSRDR3 are valid.
PAGE 1148
H8S/2456, H8S/2456R, H8S/2454 Group Section 20 Synchronous Serial Communication Unit (SSU) 20.4 Operation 20.4.1 Transfer Clock A transfer clock can be selected from eight internal clocks and an external clock. When using this module, set the SCKS bit in SSCRH to 1 to select the SSCK pin as a serial clock. When the MSS bit in SSCRH is 1, an internal clock is selected and the SSCK pin is used as an output pin.
PAGE 1149
H8S/2456, H8S/2456R, H8S/2454 Group 20.4.3 Section 20 Synchronous Serial Communication Unit (SSU) Relationship between Data Input/Output Pins and Shift Register The connection between data input/output pins and the SS shift register (SSTRSR) depends on the combination of the MSS and BIDE bits in SSCRH and the SSUMS bit in SSCRL. Figure 20.3 shows the relationship.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 20 Synchronous Serial Communication Unit (SSU) 20.4.4 Communication Modes and Pin Functions The SSU switches the input/output pin (SSI, SSO, SSCK, and SCS) functions according to the communication modes and register settings. When a pin is used as an input pin, clear the corresponding bit in each data direction register (DDR) to 0. The relationship of communication modes and input/output pin functions are shown in tables 20.4 to 20.6. Table 20.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 20 Synchronous Serial Communication Unit (SSU) Table 20.5 Communication Modes and Pin States of SSCK Pin Communication Mode SSU communication mode Register Setting Pin State SSUMS MSS SCKS SSCK 0 0 0 ⎯ 1 Input 0 ⎯ 1 Output 0 ⎯ 1 Input 0 ⎯ 1 Output 1 Clock synchronous 1 communication mode 0 1 [Legend] ⎯: Not used as SSU pin Table 20.
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Section 20 Synchronous Serial Communication Unit (SSU) 20.4.5 H8S/2456, H8S/2456R, H8S/2454 Group SSU Mode In SSU mode, data communications are performed via four lines: clock line (SSCK), data input line (SSI or SSO), data output line (SSI or SSO), and chip select line (SCS). In addition, the SSU supports bidirectional mode in which a single pin functions as data input and data output lines. (1) Initial Settings in SSU Mode Figure 20.4 shows an example of the initial settings in SSU mode.
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H8S/2456, H8S/2456R, H8S/2454 Group (2) Section 20 Synchronous Serial Communication Unit (SSU) Data Transmission Figure 20.5 shows an example of transmission operation, and figure 20.6 shows a flowchart example of data transmission. When transmitting data, the SSU operates as shown below. In master mode, the SSU outputs a transfer clock and data.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 20 Synchronous Serial Communication Unit (SSU) 1 frame SCS 1 frame SSCK SSO Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 7 SSTDR0 (LSB first transmission) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSTDR0 (MSB first transmission) TDRE TEND LSI operation User operation TXI interrupt generated TEI interrupt generated TXI interrupt generated TEI interrupt generated Data written to SSTDR0 Data written to SSTDR0 Figure 20.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 20 Synchronous Serial Communication Unit (SSU) 1 frame SCS SSCK SSO (LSB first) Bit 0 Bit 1 SSO (MSB first) Bit 7 Bit 6 Bit 6 to Bit 7 Bit 0 Bit 1 Bit 0 Bit 7 Bit 6 SSTDR2 Bit 1 to to Bit 6 Bit 7 Bit 0 Bit 1 Bit 0 Bit 7 Bit 6 SSTDR1 SSTDR0 to to Bit 6 Bit 7 Bit 1 Bit 0 SSTDR0 Bit 1 SSTDR1 to SSTDR2 TDRE TEND TXI interrupt generated LSI operation User operation TEI interrupt generated Data written to SSTDR0, SSTDR1, and S
PAGE 1156
Section 20 Synchronous Serial Communication Unit (SSU) Start [1] Initial setting [2] Read TDRE in SSSR TDRE = 1? [1] Initial setting: Specify the transmit data format. No Write transmit data to SSTDR TDRE automatically cleared [4] Procedure for data transmission end: To end data transmission, confirm that the TEND bit is cleared to 0. After completion of transmitting the last bit, clear the TE bit to 0.
PAGE 1157
H8S/2456, H8S/2456R, H8S/2454 Group (3) Section 20 Synchronous Serial Communication Unit (SSU) Data Reception Figure 20.7 shows an example of reception operation, and figure 20.8 shows a flowchart example of data reception. When receiving data, the SSU operates as shown below. After setting the RE bit to 1 and dummy-reading SSRDR, the SSU starts data reception. In master mode, the SSU outputs a transfer clock and receives data.
PAGE 1158
H8S/2456, H8S/2456R, H8S/2454 Group Section 20 Synchronous Serial Communication Unit (SSU) 1 frame SCS SSCK SSI (LSB first) Bit 0 Bit 1 Bit 2 SSO (MSB first) Bit 7 Bit 6 Bit 5 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 3 SSRDR1 Bit 4 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 2 Bit 1 Bit 0 SSRDR0 SSRDR0 Bit 4 Bit 3 SSRDR1 RDRF RXI interrupt generated LSI operation User operation Dummy-read SSRDR0 and SSRDR1 Figure 20.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 20 Synchronous Serial Communication Unit (SSU) 1 frame SCS SSCK SSI (LSB first) Bit 0 SSI (MSB first) Bit 7 to Bit 7 SSRDR3 to Bit 0 SSRDR0 Bit 0 to Bit 7 Bit 0 SSRDR2 Bit 7 to Bit 0 to Bit 7 SSRDR1 Bit 7 SSRDR1 to Bit 0 SSRDR2 Bit 0 to Bit 7 SSRDR0 Bit 7 to Bit 0 SSRDR3 RDRF LSI operation User operation RXI interrupt generated Dummy-read SSRDR0, SSRDR1, SSRDR2 and SSRDR3 Figure 20.
PAGE 1160
Section 20 Synchronous Serial Communication Unit (SSU) H8S/2456, H8S/2456R, H8S/2454 Group Start [1] Initial setting [2] Dummy-read SSRDR [1] Initial setting: Specify the receive data format. [2] Start reception: When SSRDR is dummy-read with RE = 1, reception is started. Read SSSR No RDRF = 1? Yes ORER = 1? Yes No Consecutive data reception? Yes [4] [3] [3], [6] Receive error processing: When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR.
PAGE 1161
H8S/2456, H8S/2456R, H8S/2454 Group (4) Section 20 Synchronous Serial Communication Unit (SSU) Data Transmission/Reception Figure 20.9 shows a flowchart example of simultaneous transmission/reception. The data transmission/reception is performed combining the data transmission and data reception as mentioned above. The data transmission/reception is started by writing transmit data to SSTDR with TE = RE = 1.
PAGE 1162
H8S/2456, H8S/2456R, H8S/2454 Group Section 20 Synchronous Serial Communication Unit (SSU) Start [1] Initial setting [2] Read TDRE in SSSR [1] Initial setting: Specify the transmit/receive data format. No TDRE = 1? Yes Write transmit data to SSTDR [3] Check the SSU state: Read SSSR confirming that the RDRF bit is 1. A change of the RDRF bit (from 0 to 1) can be notified by RXI interrupt.
PAGE 1163
H8S/2456, H8S/2456R, H8S/2454 Group Section 20 Synchronous Serial Communication Unit (SSU) SCS Pin Control and Conflict Error 20.4.6 When bits CSS1 and CSS0 in SSCRH are specified to B'10 and the SSUMS bit in SSCRL is cleared to 0, the SCS pin functions as an input (Hi-Z) to detect conflict error. The conflict detection period is from setting the MSS bit in SSCRH to 1 to starting serial transfer and after transfer ends.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 20 Synchronous Serial Communication Unit (SSU) 20.4.7 Clock Synchronous Communication Mode In clock synchronous communication mode, data communications are performed via three lines: clock line (SSCK), data input line (SSI), and data output line (SSO). (1) Initial Settings in Clock Synchronous Communication Mode Figure 20.12 shows an example of the initial settings in clock synchronous communication mode.
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H8S/2456, H8S/2456R, H8S/2454 Group (2) Section 20 Synchronous Serial Communication Unit (SSU) Data Transmission Figure 20.13 shows an example of transmission operation, and figure 20.14 shows a flowchart example of data transmission. When transmitting data in clock synchronous communication mode, the SSU operates as shown below. In master mode, the SSU outputs a transfer clock and data.
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Section 20 Synchronous Serial Communication Unit (SSU) Start [1] Initial setting [2] Read TDRE in SSSR TDRE = 1? [4][1] Initial setting: Specify the transmit data format. No Write transmit data to SSTDR TDRE automatically cleared [4] Procedure for data transmission end: To end data transmission, confirm that the TEND bit is cleared to 0. After completion of transmitting the last bit, clear the TE bit to 0.
PAGE 1167
H8S/2456, H8S/2456R, H8S/2454 Group (3) Section 20 Synchronous Serial Communication Unit (SSU) Data Reception Figure 20.15 shows an example of reception operation, and figure 20.16 shows a flowchart example of data reception. When receiving data, the SSU operates as shown below. After setting the RE bit in SSER to 1, the SSU starts data reception. In master mode, the SSU outputs a transfer clock and receives data.
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Section 20 Synchronous Serial Communication Unit (SSU) [1] Start Read SSSR No RDRF = 1? Yes ORER = 1? Initial setting: Specify the receive data format. [2], [4] Receive error processing: When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR. After that, clear the ORER bit to 0. While the ORER bit is set to 1, transmission or reception is not resumed.
PAGE 1169
H8S/2456, H8S/2456R, H8S/2454 Group (4) Section 20 Synchronous Serial Communication Unit (SSU) Data Transmission/Reception Figure 20.17 shows a flowchart example of simultaneous transmission/reception. The data transmission/reception is performed combining the data transmission and data reception as mentioned above. The data transmission/reception is started by writing transmit data to SSTDR with TE = RE = 1.
PAGE 1170
H8S/2456, H8S/2456R, H8S/2454 Group Section 20 Synchronous Serial Communication Unit (SSU) Start [1] Initial setting [2] Read TDRE in SSSR [1] Initial setting: Specify the transmit/receive data format. No TDRE = 1? Yes Write transmit data to SSTDR [2] Check the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit in SSSR is 1. The TDRE bit is automatically cleared to 0 and transmission is started by writing data to SSTDR.
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H8S/2456, H8S/2456R, H8S/2454 Group 20.5 Section 20 Synchronous Serial Communication Unit (SSU) Interrupt Requests The SSU interrupt requests are an overrun error, a conflict error, a receive data register full, transmit data register empty, and a transmit end interrupts.
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Section 20 Synchronous Serial Communication Unit (SSU) 20.6 Usage Note 20.6.1 Module Stop Function Setting H8S/2456, H8S/2456R, H8S/2454 Group SSU operation can be disabled or enabled using the module stop control register. The initial setting is for the SSU operation is to be halted. Register access is enabled by clearing the module stop state. For details, see section 24, Power-Down Modes. Page 1142 of 1408 R01UH0309EJ0500 Rev. 5.
PAGE 1173
H8S/2456, H8S/2456R, H8S/2454 Group Section 21 RAM Section 21 RAM This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on the system control register (SYSCR), see section 3.2.2, System Control Register (SYSCR).
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Section 21 RAM Page 1144 of 1408 H8S/2456, H8S/2456R, H8S/2454 Group R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory Section 22 Flash Memory The flash memory in this LSI can be accessed in three programming modes: user programming mode, boot mode, and programmer mode. Table 22.1 gives an overview of the flash memory specifications (see section 1, Overview, for items that are not shown in table 22.1). Table 22.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory Table 22.2 Overview of Flash Memory Programming Modes On-board Programming Mode Item Functional overview Off-board Mode User Programming Mode Boot Mode The user ROM is programmed by the CPU through execution of software commands. The user ROM is programmed The user ROM is through the on-chip SCI programmed through a interface. dedicated parallel programmer.
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H8S/2456, H8S/2456R, H8S/2454 Group 22.1 Section 22 Flash Memory Memory Map This ROM is divided into the user ROM and the data flash. Figure 22.1 shows a block diagram of the flash memory. The user ROM and data flash are divided into multiple blocks. The user ROM can be programmed in user programming mode, boot mode, or programmer mode.
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Section 22 Flash Memory 22.2 H8S/2456, H8S/2456R, H8S/2454 Group Register Descriptions The flash memory has the following registers. • Flash memory control register 1 (FLMCR1) • Flash memory data block protect register (FLMDBPR) • Flash memory status register (FLMSTR) Note: When the FLSHE bit in SYSCR is 0, the read values are undefined and registers cannot be modified. Page 1148 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory 22.2.1 Flash Memory Control Register 1 (FLMCR1) Bit Bit Name Initial Value R/W 7 ⎯ 0 ⎯ Description Reserved The initial value should not be changed. 6 CBIDB 1 R/W CPU Programming Mode Select Setting this bit to 0 (CPU programming mode) enables command acceptance. 0: CPU programming mode enabled 1: CPU programming mode disabled 5 ⎯ 0 ⎯ Reserved The initial value should not be changed.
PAGE 1180
H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory 22.2.2 Flash Memory Data Block Protect Register (FLMDBPR) Bit Bit Name Initial Value R/W 7 ⎯ 0 ⎯ Description Reserved The initial value should not be changed. ⎯ 6 0 ⎯ Reserved The initial value should not be changed. 5 ⎯ 0 ⎯ 4 ⎯ 0 ⎯ Reserved The initial value should not be changed. Reserved The initial value should not be changed. ⎯ 3 0 ⎯ Reserved The initial value should not be changed.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory 22.2.3 Flash Memory Status Register (FLMSTR) Bit Bit Name Initial Value R/W 7 ⎯ 0 ⎯ Description Reserved The initial value should not be changed. ⎯ 6 0 ⎯ Reserved The initial value should not be changed. 5 FMERSF* 0 R Erase or Blank Check Status Flag 0: Successfully completed 1: Ended with an error ⎯ 4 0 ⎯ Reserved The initial value should not be changed.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory 22.3 On-Board Programming Mode When the mode pins (MD0, MD1, and MD2) are set to on-board programming mode and the reset start is executed, a transition is made to on-board programming mode in which the on-chip flash memory can be programmed/erased. On-board programming mode has three operating modes: SCI boot mode by P27 and P26 settings, USB boot mode, and user programming mode. Table 22.3 shows the pin setting for each operating mode.
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H8S/2456, H8S/2456R, H8S/2454 Group 22.3.1 Section 22 Flash Memory User Programming Mode In the user programming mode, the flash memory can be programmed by the CPU through execution of software commands. In this mode, the user ROM and data flash can be programmed without using a ROM programmer with the microcomputer mounted on a system board. The programming and block erase commands should be executed only in each block area of the user ROM and data flash.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory 22.3.2 EW0 Mode Setting the FMCMDEN bit in FLMCR1 to 1 shifts the flash memory into the user programming mode, in which commands can be accepted. Figure 22.2 shows how to set and clear the EW0 mode. Programming and erasure are controlled through software commands. The flash memory state after programming or erasure can be checked through FLMSTR or the status register.
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H8S/2456, H8S/2456R, H8S/2454 Group 22.4 Section 22 Flash Memory Software Commands The following describes the software commands. A command or data should be read or written in 16-bit units at an even address in the user ROM or data flash area. When a command code is written, the lower eight bits (D7 to D0) are ignored. Table 22.
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Section 22 Flash Memory 22.4.1 H8S/2456, H8S/2456R, H8S/2454 Group Read Array This command reads the flash memory. Write H'FFxx in the first bus cycle to shift the flash memory into the read array mode. Specify the target read address in the next bus cycle after setting the CBIDB bit in FLMCR1 to 1, and data is read from the address in 16-bit units. As the flash memory stays in the read array mode until another command is issued, multiple addresses can be read in sequence. 22.4.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory After automatic writing is completed, the result can be checked through the FMPRSF bit in FMRSTR (see section 22.6, Full Status Check). Once an address is programmed, no additional data can be written to the address. Figure 22.3 shows a flowchart of the program command processing. In the EW0 mode, the read status register mode is entered as soon as automatic writing starts, and the status register can be read.
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Section 22 Flash Memory 22.4.5 H8S/2456, H8S/2456R, H8S/2454 Group Block Erase Write H'20xx in the first bus cycle and H'D0xx to the lowest address (an even address) of the target block in the second cycle; automatic erasure (erasing data and verifying the erased status) starts in the specified block. Completion of automatic erasure can be checked through the FMRDY bit in FLMSTR. The FMRDY bit is 0 (busy) during automatic erasure and becomes 1 (ready) when erasure is completed.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory Start Write command code "H'20xx"*1 Write "H'D0xx" to the lowest address of the block. NO FMRDY = 1? YES Full status check *2*3 End of block erase Notes:1. Write the command code and data to even addresses. 2. See figure 22.8. 3. If an erase error occurs, repeat a sequence of the clear status register command -> block erase command at least three times until no erase error occurs. Figure 22.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory 22.4.6 Block Blank Check This command checks if a block is blank (the erased state). Write H'25xx in the first bus cycle and H'D0xx to the lowest address (an even address) of the target block in the second cycle; the check result will be stored in the FMERSF bit in FLMSTR. After the FMRDY bit in FLMSTR has become 1 (ready), read the FMERSF bit. Figure 22.5 shows a flowchart of the block blank check command processing.
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H8S/2456, H8S/2456R, H8S/2454 Group 22.5 Section 22 Flash Memory Status Register The status register indicates the state of flash memory operation and whether erasure or programming has ended successfully or with an error. The status register contents can be read through the FMRDY, FMPRSF, and FMERSF bits in FLMSTR. Table 22.6 shows the status register. In the EW0 mode, the status register can be read with the following timing.
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Section 22 Flash Memory 22.5.1 H8S/2456, H8S/2456R, H8S/2454 Group Sequencer Status (FMRDY Bit) The sequencer status bit indicates the state of flash memory operation. Its value is 0 during execution of a program, block erase, or block blank check, and 1 in other cases. 22.5.2 Erase Status (FMERSF Bit) See section 22.6, Full Status Check. 22.5.3 Programming Status (FMPRSF Bit) See section 22.6, Full Status Check. Page 1162 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group 22.6 Section 22 Flash Memory Full Status Check When an error occurs, the FMERSF or FMPRSF bit in FLMSTR becomes 1 to indicate occurrence of the error. Read these status bits (full status check) to check the operation results. Table 22.7 shows the errors and FLMSTR status and figure 22.6 shows a flowchart of full status check processing and corrective actions for each error. Table 22.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory Full status check FMPRSF = 1 and FMERSF =1 ? YES Command sequence error . . . (1) Execute a clear status register command to clear the FMPRSF and FMERSF bits to 0 (successfully completed state). (2) Check if the command was input correctly, and execute it again. NO FMERSF = 0? NO Erase error . . . (1) Execute a clear stats register command to clear the FMERSF bit to 0 (successfully completed state). (2) Execute a block erase command.
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H8S/2456, H8S/2456R, H8S/2454 Group 22.7 Notes on User Programming Mode 22.7.1 Prohibited Interrupts (EW0 Mode) Section 22 Flash Memory The NMI and watchdog timer interrupts can be used because FLMCR1 is forcibly initialized when an interrupt is generated; specify the destination address of each interrupt routine in the fixed vector table. Flash memory programming is terminated when an NMI interrupt or a watchdog timer interrupt occurs.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory 22.9 SCI Boot Mode SCI boot mode executes programming/erasing of the user ROM by means of the control command and program data transmitted from the externally connected host via the on-chip SCI_1. In SCI boot mode, the tool for transmitting the control command and program data, and the program data must be prepared in the host. The serial communication mode is set to asynchronous mode.
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H8S/2456, H8S/2456R, H8S/2454 Group 22.10 Section 22 Flash Memory USB Boot Mode USB boot mode executes programming/erasing of the user ROM by means of the control command and program data transmitted from the externally connected host via the USB. In USB boot mode, the tool for transmitting the control command and program data, and the program data must be prepared in the host. The system configuration in USB boot mode is shown in figure 22.8. Interrupts are ignored in USB boot mode.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory (1) Features • Bus power mode and self-power mode are selectable. • The P20 pin supports the D+ pull-up control connection. • For enumeration information, refer to table 22.8. Table 22.8 Enumeration Information USB standard Ver.2.
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H8S/2456, H8S/2456R, H8S/2454 Group (2) Section 22 Flash Memory State Transition Diagram The state transition after USB boot mode is initiated is shown in figure 22.9. Boot mode initiation (reset by boot mode) Enumeration H'55 1. n eptio rec Inquiry command reception 2. Wait for inquiry setting command Processing of inquiry setting command Inquiry command response 3. 4.
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Section 22 Flash Memory 4. (3) H8S/2456, H8S/2456R, H8S/2454 Group After all user ROMs are automatically erased, the state of waiting for programming/erasing command is entered. When the programming command is received, the state shifts to the state of waiting for programming data. The same applies to erasing.
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H8S/2456, H8S/2456R, H8S/2454 Group 22.11 Section 22 Flash Memory Serial Communication Interface Specification for Boot Mode Initiating boot mode enables the boot program to communicate with the host by using the on-chip SCI_1. The serial communication interface specification is shown below. (1) Status The boot program has three states. 1. Bit-Rate-Adjustment State In this state, the boot program adjusts the bit rate to communicate with the host.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory These boot program states are shown in figure 22.10. Reset Bit-rate-adjustment state Inquiry/response wait Response Inquiry Operations for inquiry and selection Transition to programming/erasing Operations for response Operations for erasing user MATs Programming/erasing wait Programming Operations for programming Erasing Operations for erasing Checking Operations for checking Figure 22.
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H8S/2456, H8S/2456R, H8S/2454 Group (2) Section 22 Flash Memory Bit-Rate-Adjustment State The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate has been adjusted, the boot program enters the inquiry and selection state. The bit-rate-adjustment sequence is shown in figure 22.11.
PAGE 1204
Section 22 Flash Memory (3) H8S/2456, H8S/2456R, H8S/2454 Group Communications Protocol After adjustment of the bit rate, the protocol for communications between the host and the boot program is as shown below. 1. One-byte commands and one-byte responses These commands and responses are comprised of a single byte. These are consists of the inquiries and the ACK for successful completion. 2. n-byte commands or n-byte responses These commands and responses are comprised of n bytes of data.
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H8S/2456, H8S/2456R, H8S/2454 Group One-byte command or one-byte response Section 22 Flash Memory Command or response n-byte Command or n-byte response Data Size Checksum Command or response Error response Error code Error response 128-byte programming Address Data (n bytes) Command Memory read response Size Checksum Data Response Checksum Figure 22.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory (4) Inquiry/Selection State The boot program returns information from the flash memory in response to the host’s inquiry commands and sets the device code, clock mode, and bit rate in response to the host’s selection command. Inquiry and selection commands are listed below. Table 22.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory The selection commands, which are device selection (H'10), clock mode selection (H'11), and new bit rate selection (H'3F), should be sent from the host in that order. These commands will certainly be needed. When two or more selection commands are sent at once, the last command will be valid.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory (b) Device Selection The boot program will set the supported device to the specified device code. The program will return the selected device code in response to the inquiry after this setting has been made. Command H'10 Size Device code SUM • Command, H'10, (1 byte): Device selection • Size (1 byte): Amount of device-code data This is fixed at 2.
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H8S/2456, H8S/2456R, H8S/2454 Group (d) Section 22 Flash Memory Clock Mode Selection The boot program will set the specified clock mode. The program will return the selected clockmode information after this setting has been made. The clock-mode selection command should be sent after the device-selection commands. Command H'11 Size Mode SUM • Command, H'11, (1 byte): Selection of clock mode • Size (1 byte): Amount of data that represents the modes This is fixed at 1.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory (e) Multiplication Ratio Inquiry The boot program will return the supported multiplication and division ratios.
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H8S/2456, H8S/2456R, H8S/2454 Group (f) Section 22 Flash Memory Operating Clock Frequency Inquiry The boot program will return the number of operating clock frequencies, and the maximum and minimum values.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory (g) User ROM Information Inquiry The boot program will return the number of user ROMs and their addresses.
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H8S/2456, H8S/2456R, H8S/2454 Group (h) Section 22 Flash Memory Erased Block Information Inquiry The boot program will return the number of erased blocks and their addresses.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory (j) New Bit-Rate Selection The boot program will set a new bit rate and return the new bit rate. This selection should be sent after sending the clock mode selection command.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory • SUM (1 byte): Checksum Response H'06 • Response, H'06, (1 byte): Response to selection of a new bit rate When it is possible to set the bit rate, the response will be ACK. Error Response H'BF ERROR • Error response, H'BF, (1 byte): Error response to selection of new bit rate • ERROR: (1 byte): Error code H'11: Sum check error H'24: Bit-rate selection disable error The rate is not available.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory The calculated operating frequency should be checked to ensure that it is within the range of minimum to maximum frequencies which are available with the clock modes of the specified device. When it is out of this range, an operating frequency error is generated. 4.
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H8S/2456, H8S/2456R, H8S/2454 Group (6) Section 22 Flash Memory Transition to Programming/Erasing State The boot program will transfer the erasing program, and erase data of the user ROMs. On completion of this erasure, ACK will be returned and the programming/erasing state will be entered.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory (7) Command Error A command error will occur when a command is undefined, the order of commands is incorrect, or a command is unacceptable. Issuing a clock-mode selection command before a device selection or an inquiry command after the transition to programming/erasing state command, are examples.
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H8S/2456, H8S/2456R, H8S/2454 Group (9) Section 22 Flash Memory Programming/Erasing State A programming selection command makes the boot program select the programming method, an 128-byte programming command makes it program the memory with data, and an erasing selection command and block erasing command make it erase the block. The programming/ erasing commands are listed below. Table 22.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory Where the sequence of programming operations that is executed includes programming with another method or of another ROM, the procedure must be repeated from the programming selection command. The sequence for programming-selection and 128-byte programming commands is shown in figure 22.14.
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H8S/2456, H8S/2456R, H8S/2454 Group (b) Section 22 Flash Memory 128-Byte Programming The boot program will use the programming program transferred by the programming selection to program the user ROMs in response to 128-byte programming. Command H'50 Address Data ··· ··· SUM • Command, H'50, (1 byte): 128-byte programming • Programming address (4 bytes): Start address for programming Multiple of the size specified in response to the programming unit inquiry (i.e.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory (c) Programming End Sending the 128-byte programming command with the address of H'FFFFFFFF will stop the programming operation. The boot program will interpret this as the end of the programming and wait for selection of programming or erasing. Command H'50 Address SUM • Command, H'50, (1 byte): 128-byte programming • Programming address (4 bytes): End code is H'FF, H'FF, H'FF, H'FF.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory (10) Erasure Erasure is performed with the erasure selection and block erasure command. Firstly, erasure is selected by the erasure selection command and the boot program then erases the specified block. The command should be repeatedly executed if two or more blocks are to be erased. Sending a block-erasure command from the host with the block number H'FF will stop the erasure operating.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory (a) Erasure Selection The boot program will transfer the erasure program. User ROM data is erased by the transferred erasure program. Command H'48 • Command, H'48, (1 byte): Erasure selection Response H'06 • Response, H'06, (1 byte): Response for erasure selection After the erasure program has been transferred, the boot program will return ACK.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory (11) Memory Read The boot program will return the data stored in the specified address in response to a memory read command. Command H'52 Size Area Read size Read address SUM • Command, H'52, (1 byte): Memory read • Size (1 byte): Amount of data that represents the area, read address, and read size (fixed at 9) • Area (1 byte): H'01: User ROM area An address error occurs when the area setting is incorrect.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory (12) User ROM Sum Check The boot program will add all the data bytes in the user ROM area and return the result in response to a user ROM sum check command. Command H'4B • Command, H'4B, (1 byte): Sum check for user ROM Response H'5B Size Checksum of user ROM SUM • Response, H'5B, (1 byte): Response to the user ROM sum check • Size (1 byte): The number of bytes that represents the checksum This is fixed to 4.
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H8S/2456, H8S/2456R, H8S/2454 Group Response Section 22 Flash Memory H'06 • Response, H'06, (1 byte): Response to the user ROM blank check If all user ROM areas are blank (H'FF), the boot program will return ACK.
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Section 22 Flash Memory H8S/2456, H8S/2456R, H8S/2454 Group Table 22.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 22 Flash Memory • ERROR (1 byte): Error status ERROR = 0 indicates normal operation. ERROR = 1 indicates error has occurred. Table 22.
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Section 22 Flash Memory 22.12 H8S/2456, H8S/2456R, H8S/2454 Group Programmer Mode Along with the on-board programming mode, this LSI also has a programmer mode as a further mode for the writing and erasing of programs and data. In the programmer mode, a generalpurpose PROM programmer can be used to freely write programs to the on-chip ROM. Program/erase is possible on the user ROM. The PROM programmer must support Renesas microcomputers with 256-Kbyte flash memory as a device type.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 23 Clock Pulse Generator Section 23 Clock Pulse Generator This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (φ) and internal clocks. The clock pulse generator consists of an oscillator circuit, a system-clock PLL circuit and a divider. Figure 23.1 shows a block diagram of the clock pulse generator.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 23 Clock Pulse Generator 23.1 Register Descriptions The clock pulse generator has the following registers. • System clock control register (SCKCR) • PLL control register (PLLCR) • USB PLL control register (USPLLCR) 23.1.1 System Clock Control Register (SCKCR) SCKCR controls φ clock output and selects operation when the PLLCR register setting is changed.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 23 Clock Pulse Generator Bit Bit Name Initial Value R/W Description 5 SDPSTP* 0 R/W SDRAMφ Output Disable Controls SDRAMφ. 0: SDRMφ output. 1: Can be used as PH1/CS5/RAS5. When the SDRAMφ output is selected, the pin functions as follows in each power-down mode.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 23 Clock Pulse Generator 23.1.2 PLL Control Register (PLLCR) PLLCR sets the frequency multiplication factor used by the system-clock PLL circuit. Care must be taken when writing to this register. For details, see section 23.3, System-Clock PLL Circuit and Divider. Bit Bit Name Initial Value R/W Description 7 to 4 ⎯ All 0 ⎯ Reserved These bits are always read as 0 and cannot be modified. 3 ⎯ 0 R/W Reserved This bit can be read from or written to.
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H8S/2456, H8S/2456R, H8S/2454 Group 23.1.3 Section 23 Clock Pulse Generator USB PLL Control Register (USPLLCR) USPLLCR selects multiplication factor used by the PLL circuit. Bit Bit Name Initial Value R/W Description 7 to 2 ⎯ All 0 ⎯ Reserved These bits are always read as 0 and cannot be modified. 1 USSTC1 0 R/W 0 USSTC0 0 R/W Frequency Multiplication Factor for USB PLL Circuit Setting The USSTC bits specify the frequency multiplication factor for USB PLL circuit.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 23 Clock Pulse Generator 23.2 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 23.2.1 Connecting a Crystal Resonator A crystal resonator can be connected as shown in the example in figure 23.2. Select the damping resistance Rd according to table 23.1. When a crystal resonator is used, the range of its frequencies is from 8 to 20 MHz. Figure 23.3 shows the equivalent circuit of the crystal resonator.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 23 Clock Pulse Generator Table 23.2 Crystal Resonator Characteristics Frequency (MHz) 8 12 16 20 RS max (Ω) 80 60 50 40 C0 max (pF) 7 7 7 7 23.2.2 External Clock Input An external clock signal can be input as shown in the examples in figure 23.4. If the XTAL pin is left open, make sure that parasitic capacitance is no more than 10 pF. When the counter clock is input to the XTAL pin, make sure that the external clock is held high in standby mode.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 23 Clock Pulse Generator Table 23.3 External Clock Input Conditions Vcc = 3.0 V to 3.6 V Item Symbol Min Max Unit Test Conditions External clock input low pulse width tEXL 20 ⎯ ns Figure 23.5 External clock input high pulse width tEXH 20 ⎯ ns External clock rise time tEXr ⎯ 5 ns External clock fall time tEXf ⎯ 5 ns Clock low pulse width tCL 0.4 0.6 tcyc Clock high pulse width tCH 0.4 0.6 tcyc tEXH tEXL EXTAL VCC × 0.
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H8S/2456, H8S/2456R, H8S/2454 Group 23.3 Section 23 Clock Pulse Generator System-Clock PLL Circuit and Divider The system-clock PLL circuit and divider have the function of multiplying the frequency of the clock from the oscillator by a factor of 1, 2, or dividing by 2. The system clock frequency is set with the STC1 and STC0 bits in PLLCR. The phase of the rising edge of the internal clock is controlled so as to match that of the rising edge of the EXTAL pin.
PAGE 1240
H8S/2456, H8S/2456R, H8S/2454 Group Section 23 Clock Pulse Generator 23.4 PLL Circuit for the USB Module The PLL circuit for the USB module takes 8, 12, and 16 MHz clock signals from an oscillator and generates the 48-MHz clock for the USB module through frequency-multiplication by 3, 4, or 6. The frequency-multiplication factor is set by bits USSTC1 and USSTC0 in the USPLLCR. For details on the USPLLCR, see section 23.1.3, USB PLL Control Register (USPLLCR).
PAGE 1241
H8S/2456, H8S/2456R, H8S/2454 Group 23.5 Usage Notes 23.5.1 Notes on Clock Pulse Generator Section 23 Clock Pulse Generator 1. The following points should be noted since the frequency of φ changes according to the settings of PLLCR. Select a clock division ratio that is within the operation guaranteed range of clock cycle time tcyc shown in the AC timing of the Electrical Characteristics. In other words, φ must be set to a value between 8 MHz (minimum) and 33 MHz (maximum).
PAGE 1242
H8S/2456, H8S/2456R, H8S/2454 Group Section 23 Clock Pulse Generator 23.5.3 Notes on Board Design When using the crystal resonator, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Other signal lines should be routed away from the oscillation circuit to prevent induction from interfering with correct oscillation. See figure 23.6. Prohibited Signal A Signal B This LSI CL2 XTAL EXTAL CL1 Figure 23.
PAGE 1243
H8S/2456, H8S/2456R, H8S/2454 Group Section 24 Power-Down Modes Section 24 Power-Down Modes In addition to the normal program execution state, this LSI has power-down modes in which operation of the CPU and oscillator is halted and power consumption is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip peripheral modules, and so on.
PAGE 1244
H8S/2456, H8S/2456R, H8S/2454 Group Section 24 Power-Down Modes Table 24.
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H8S/2456, H8S/2456R, H8S/2454 Group Operating State Peripheral RAM functions I/O Notes: 1. 2. 3. 4. 5. 6.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 24 Power-Down Modes STBY pin = low Reset state STBY pin = high RES pin = low Hardware standby mode RES pin = high SSBY = 0 SLEEP instruction High-speed mode (Internal clock is PLL circuit output clock) STC1, STC0 ≠ 11 STC1, STC0 = 11 Clock division mode SLEEP instruction MSTPCR = H'FFFF (H'FFFE), EXMSTPCR = H'FFFF, SSBY = 0 Interrupt*1 All module-clocks-stop mode Any interrupt SLEEP instruction External interrupt*2 Program execution state : Transiti
PAGE 1247
H8S/2456, H8S/2456R, H8S/2454 Group 24.1 Section 24 Power-Down Modes Register Descriptions The registers relating to the power-down mode are shown below. For details on the PLL control register (PLLCR), see section 23.1.2, PLL Control Register (PLLCR).
PAGE 1248
H8S/2456, H8S/2456R, H8S/2454 Group Section 24 Power-Down Modes Bit Bit Name Initial Value R/W Description 5 ⎯ 0 ⎯ Reserved This bit is always read as 0. The initial value should not be changed. 4 ⎯ 0 ⎯ Reserved This bit is always read as 0. The write value should always be 0.
PAGE 1249
H8S/2456, H8S/2456R, H8S/2454 Group 24.1.2 Section 24 Power-Down Modes Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) MSTPCR performs module stop state control. Setting a bit to 1, the corresponding module enters the module stop state, while clearing the bit to 0 clears the module stop state.
PAGE 1250
H8S/2456, H8S/2456R, H8S/2454 Group Section 24 Power-Down Modes • MSTPCRL Bit Bit Name Initial Value R/W Module 7 MSTP7 1 R/W A/D converter unit 1 6 MSTP6 1 R/W A/D converter unit 0 5 MSTP5 1 R/W Serial communication interface 4 (SCI_4) 4 MSTP4 1 R/W Serial communication interface 3 (SCI_3) 3 MSTP3 1 R/W Serial communication interface 2 (SCI_2) 2 MSTP2 1 R/W Serial communication interface 1 (SCI_1) 1 MSTP1 1 R/W Serial communication interface 0 (SCI_0) 0 MSTP0 1
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H8S/2456, H8S/2456R, H8S/2454 Group Section 24 Power-Down Modes • EXMSTPCRL Bit Bit Name Initial Value R/W Module 7 MSTP23 1 R/W Synchronous serial communication unit (SSU) 6 MSTP22 1 R/W I2C bus interface 2_3 (IIC2_3) 5 MSTP21 1 R/W I2C bus interface 2_2 (IIC2_2) 4 MSTP20 1 R/W I2C bus interface 2_1 (IIC2_1) 3 MSTP19 1 R/W I2C bus interface 2_0 (IIC2_0) 2 MSTP18 1 R/W USB function module (USB) (system clock) 1 MSTP17 1 R/W USB function module (USB) (48 MHz clock) 0
PAGE 1252
H8S/2456, H8S/2456R, H8S/2454 Group Section 24 Power-Down Modes • RMMSTPCRL Bit Bit Name Initial Value R/W Module 7 MSTP39 0 R/W On-chip RAM_7 (H'FEC000 to H'FEDFFF)* 6 MSTP38 0 R/W On-chip RAM_6 (H'FEE000 to H'FEFFFF)* 5 MSTP37 0 R/W On-chip RAM_5 (H'FF0000 to H'FF1FFF) 4 MSTP36 0 R/W On-chip RAM_4 (H'FF2000 to H'FF3FFF) 3 MSTP35 0 R/W On-chip RAM_3 (H'FF4000 to H'FF5FFF) 2 MSTP34 0 R/W On-chip RAM_2 (H'FF6000 to H'FF7FFF) 1 MSTP33 0 R/W On-chip RAM_1 (H'FF8000 to H
PAGE 1253
H8S/2456, H8S/2456R, H8S/2454 Group 24.2 Operation 24.2.1 Clock Division Mode Section 24 Power-Down Modes When bits STC1 and STC0 in PLLCR are set to 11, a transition is made to clock division mode, and the system clock frequency is divided with respect to the oscillator frequency. Clock division mode is cancelled by clearing bits STC1 and STC0 to a value other than 11. The timings of transition and clearing depend on the STCS bit setting in SCKCR.
PAGE 1254
Section 24 Power-Down Modes 24.2.2 (1) H8S/2456, H8S/2456R, H8S/2454 Group Sleep Mode Transition to Sleep Mode When the SLEEP instruction is executed while the SSBY bit is 0 in SBYCR, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are retained. Other peripheral functions do not stop. (2) Exiting Sleep Mode Sleep mode is exited by any interrupt, or signals at the RES, or STBY pins.
PAGE 1255
H8S/2456, H8S/2456R, H8S/2454 Group 24.2.3 (1) Section 24 Power-Down Modes Software Standby Mode Transition to Software Standby Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip peripheral functions, and oscillator all stop.
PAGE 1256
H8S/2456, H8S/2456R, H8S/2454 Group Section 24 Power-Down Modes (3) Setting Oscillation Stabilization Time after Clearing Software Standby Mode Bits STS3 to STS0 in SBYCR should be set as described below. • Using a Crystal Resonator: Set bits STS3 to STS0 so that the standby time is more than the oscillation stabilization time. Table 24.2 shows the standby times for operating frequencies and settings of bits STS3 to STS0. • Using an External Clock: A PLL circuit stabilization time is necessary.
PAGE 1257
H8S/2456, H8S/2456R, H8S/2454 Group (4) Section 24 Power-Down Modes Software Standby Mode Application Example Figure 24.2 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, after an NMI interrupt is accepted with the NMIEG bit in INTCR cleared to 0 (falling edge specification), the NMIEG bit is set to 1 (rising edge specification).
PAGE 1258
Section 24 Power-Down Modes 24.2.4 (1) H8S/2456, H8S/2456R, H8S/2454 Group Hardware Standby Mode Transition to Hardware Standby Mode When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state.
PAGE 1259
H8S/2456, H8S/2456R, H8S/2454 Group (3) Section 24 Power-Down Modes Hardware Standby Mode Timing Figure 24.3 shows an example of hardware standby mode timing. When the STBY pin is driven low after the RES pin has been driven low, a transition is made to hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting for the oscillation stabilization time, then changing the RES pin from low to high.
PAGE 1260
H8S/2456, H8S/2456R, H8S/2454 Group Section 24 Power-Down Modes (4) Hardware Standby Mode Timing when Power Is Supplied When entering hardware standby mode immediately after the power is supplied, the RES signal must be driven low for a given period with retaining the STBY signal high. After the RES signal is canceled, drive the STBY signal low. (1) Power supply RES (2) Reset period STBY (3) Hardware standby mode Figure 24.
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H8S/2456, H8S/2456R, H8S/2454 Group 24.2.5 Section 24 Power-Down Modes Module Stop Function Module stop function can be set for individual on-chip peripheral modules. When an MSTP bit in MSTPCR, EXMSTPCR, or RMMSTPCR is set to 1, the corresponding module stops operation at the end of the bus cycle and a transition is made to module stop state. The CPU continues operating independently.
PAGE 1262
Section 24 Power-Down Modes 24.2.
PAGE 1263
H8S/2456, H8S/2456R, H8S/2454 Group Section 24 Power-Down Modes φ Clock Output Control 24.3 Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle, and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When DDR for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is set. Table 24.
PAGE 1264
H8S/2456, H8S/2456R, H8S/2454 Group Section 24 Power-Down Modes 24.4 SDRAMφ Clock Output Control Output of the SDRAMφ clock can be controlled by the SDPSTP bit in SCKCR. When the SDPSTP bit is set to 1, the SDRAMφ clock stops at the end of the bus cycle and the pin can be used as a general port. SDRAMφ clock output is enabled when the SDPSTP bit is cleared to 0 regardless of the DDR value. Table 24.5 shows the state of the SDRAMφ pin in each processing state.
PAGE 1265
H8S/2456, H8S/2456R, H8S/2454 Group 24.5 Usage Notes 24.5.1 I/O Port Status Section 24 Power-Down Modes In software standby mode, I/O port states are retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. 24.5.2 Current Dissipation during Oscillation Stabilization Standby Period Current dissipation increases during the oscillation stabilization standby period. 24.5.
PAGE 1266
Section 24 Power-Down Modes 24.5.6 H8S/2456, H8S/2456R, H8S/2454 Group Notes on Clock Division Mode The following points should be noted in clock division mode. • Select the clock division ratio by the STC1 and STC0 bits so that the frequency of φ is within the operation guaranteed range of clock cycle time tcyc shown in the Electrical Characteristics. In other words, the frequency of φ must be 8 MHz or higher; be careful not so specify φ < 8 MHz. • All the on-chip peripheral modules operate on the φ.
PAGE 1267
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Section 25 List of Registers The address list gives information on the on-chip register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. • • • Register addresses (address order) Registers are listed from the lower allocation addresses. Registers are classified by functional modules. The access size is indicated. 2.
PAGE 1268
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers 25.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock.
PAGE 1269
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Name Number Abbreviation of Bits Address Module Data Width Access States FIFO clear register 0 FCLR0 8 H'FB98 USB 8 3 FIFO clear register 1 FCLR1 8 H'FB99 USB 8 3 Endpoint stall register 0 EPSTL0 8 H'FBA0 USB 8 3 Endpoint stall register 1 EPSTL1 8 H'FBA1 USB 8 3 Stall status register 1 STLSR1 8 H'FBA9 USB 8 3 DMA transfer setting register DMAR 8 H'FBB0 USB 8 3 Configuration value regist
PAGE 1270
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Name Number Abbreviation of Bits Address Module Data Width Access States Timer mode register_6 TMDR_6 8 H'FCD1 TPU_6 16 2 Timer I/O control register H_6 TIORH_6 8 H'FCD2 TPU_6 16 2 Timer I/O control register L_6 TIORL_6 8 H'FCD3 TPU_6 16 2 Timer interrupt enable register_6 TIER_6 8 H'FCD4 TPU_6 16 2 Timer status register_6 TSR_6 8 H'FCD5 TPU_6 16 2 Timer counter_6 TCNT_6 16 H'FCD6 TPU_6 1
PAGE 1271
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Name Number Abbreviation of Bits Address Module Data Width Access States Timer counter_9 TCNT_9 16 H'FD06 TPU_9 16 2 Timer general register A_9 TGRA_9 16 H'FD08 TPU_9 16 2 Timer general register B_9 TGRB_9 16 H'FD0A TPU_9 16 2 Timer general register C_9 TGRC_9 16 H'FD0C TPU_9 16 2 Timer general register D_9 TGRD_9 16 H'FD0E TPU_9 16 2 Timer control register_10 TCR_10 8 H'FD10 TPU_10 16 2
PAGE 1272
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Name Number Abbreviation of Bits Address Module Data Width Access States Port H open drain control register PHODR 8 H'FD4B PORT 8 2 Port J open drain control register PJODR 8 H'FD4C PORT 8 2 2 ICCRA_0 8 H'FD58 IIC2_0 8 2 2 ICCRB_0 8 H'FD59 IIC2_0 8 2 I C bus control register A_0 I C bus control register B_0 2 ICMR_0 8 H'FD5A IIC2_0 8 2 2 ICIER_0 8 H'FD5B IIC2_0 8 2 I C bus status regist
PAGE 1273
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Number Abbreviation of Bits Address Module Data Width Access States 2 ICDRT_3 8 H'FD76 IIC2_3 8 2 2 I C receive data register_3 ICDRR_3 8 H'FD77 IIC2_3 8 2 Serial expansion mode register_2 SEMR_2 8 H'FDA8 SCI_2 8 2 SS control register H SSCRH 8 H'FDB0 SSU 16 2 Register Name I C transfer data register_3 SS control register L SSCRL 8 H'FDB1 SSU 16 2 SS mode register SSMR 8 H'FDB2 SSU 16 2 SS enab
PAGE 1274
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Name Number Abbreviation of Bits Address Module Data Width Access States Interrupt priority register D IPRD 16 H'FE06 INT 16 2 Interrupt priority register E IPRE 16 H'FE08 INT 16 2 Interrupt priority register F IPRF 16 H'FE0A INT 16 2 Interrupt priority register G IPRG 16 H'FE0C INT 16 2 Interrupt priority register H IPRH 16 H'FE0E INT 16 2 Interrupt priority register I IPRI 16 H'FE10 INT
PAGE 1275
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Name Number Abbreviation of Bits Address Module Data Width Access States Port C pull-up MOS control register PCPCR 8 H'FE38 PORT 8 2 Port D pull-up MOS control register PDPCR 8 H'FE39 PORT 8 2 Port E pull-up MOS control register PEPCR 8 H'FE3A PORT 8 2 Port 3 open drain control register P3ODR 8 H'FE3C PORT 8 2 Port A open drain control register PAODR 8 H'FE3D PORT 8 2 Serial mode register_3 S
PAGE 1276
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Name Number Abbreviation of Bits Address Module Data Width Access States Timer I/O control register_4 TIOR_4 8 H'FE92 TPU_4 16 2 Timer interrupt enable register_4 TIER_4 8 H'FE94 TPU_4 16 2 Timer status register_4 TSR_4 8 H'FE95 TPU_4 16 2 Timer counter_4 TCNT_4 16 H'FE96 TPU_4 16 2 Timer general register A_4 TGRA_4 16 H'FE98 TPU_4 16 2 Timer general register B_4 TGRB_4 16 H'FE9A TPU_4 16
PAGE 1277
H8S/2456, H8S/2456R, H8S/2454 Group Register Name Section 25 List of Registers Number Abbreviation of Bits Address Module Data Width Access States Address/data multiplexed I/O control MPXCR register 8 H'FECF BSC 16 2 DRAM control register L 16 H'FED0 BSC 16 2 DRAMCR DRAM access control register H DRACCRH 8 H'FED2 BSC 16 2 DRAM access control register L DRACCRL 8 H'FED3 BSC 16 2 Refresh control register REFCR 16 H'FED4 BSC 16 2 Refresh timer counter RTCNT 8 H'FED6
PAGE 1278
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Name Number Abbreviation of Bits Address Module Data Width Access States DTC enable register A DTCERA 8 H'FF28 DTC 16 2 DTC enable register B DTCERB 8 H'FF29 DTC 16 2 DTC enable register C DTCERC 8 H'FF2A DTC 16 2 DTC enable register D DTCERD 8 H'FF2B DTC 16 2 DTC enable register E DTCERE 8 H'FF2C DTC 16 2 DTC enable register F DTCERF 8 H'FF2D DTC 16 2 DTC enable register G DTCERG 8
PAGE 1279
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Number Abbreviation of Bits Address Module Data Width Access States Next data register L* NDRLL 8 H'FF4F PPG 8 2 Port 1 register PORT1 8 H'FF50 PORT 8 2 Port 2 register PORT2 8 H'FF51 PORT 8 2 Port 3 register PORT3 8 H'FF52 PORT 8 2 Port 4 register PORT4 8 H'FF53 PORT 8 2 Port 5 register PORT5 8 H'FF54 PORT 8 2 Port 6 register PORT6 8 H'FF55 PORT 8 2 Port 8 register PORT8 8 H'FF57 PORT
PAGE 1280
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Name Number Abbreviation of Bits Address Module Data Width Access States Port J data register PJDR 8 H'FF73 PORT 8 2 Port H data direction register PHDDR 8 H'FF74 PORT 8 2 Port J data direction register PJDDR 8 H'FF75 PORT 8 2 Serial mode register_0 SMR_0 8 H'FF78 SCI_0 8 2 Bit rate register_0 BRR_0 8 H'FF79 SCI_0 8 2 Serial control register_0 SCR_0 8 H'FF7A SCI_0 8 2 Transmit data regi
PAGE 1281
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Name Number Abbreviation of Bits Address Module Data Width Access States A/D control/status register_0 ADCSR_0 8 H'FFA0 A/D_0 16 2 A/D control register_0 ADCR_0 8 H'FFA1 A/D_0 16 2 D/A data register 2 DADR2 8 H'FFA8 D/A 8 2 D/A data register 3 DADR3 8 H'FFA9 D/A 8 2 D/A control register 23 DACR23 8 H'FFAA D/A 8 2 Timer control register_0 TCR_0 8 H'FFB0 TMR_0 16 2 Timer control register_
PAGE 1282
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Name Number Abbreviation of Bits Address Module Data Width Access States Port function control register 3 PFCR3 8 H'FFC8 PORT 8 2 Port function control register 4 PFCR4 8 H'FFC9 PORT 8 2 Port function control register 5 PFCR5 8 H'FFCA PORT 8 2 Timer control register_0 TCR_0 8 H'FFD0 TPU_0 16 2 Timer mode register_0 TMDR_0 8 H'FFD1 TPU_0 16 2 Timer I/O control register H_0 TIORH_0 8 H'FFD2
PAGE 1283
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Notes: 1. If the pulse output group 2 and pulse output group 3 output triggers are the same according to the PCR setting, the NDRH address will be H'FF4C, and if different, the address of NDRH for group 2 will be H'FF4E, and that for group 3 will be H'FF4C.
PAGE 1284
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers 25.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively.
PAGE 1285
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module EPDR0s D7 D6 D5 D4 D3 D2 D1 D0 USB EPDR1 D7 D6 D5 D4 D3 D2 D1 D0 EPDR2 D7 D6 D5 D4 D3 D2 D1 D0 EPDR3 D7 D6 D5 D4 D3 D2 D1 D0 EPSZ0o ⎯ ⎯ ⎯ D4 D3 D2 D1 D0 EPSZ1 ⎯ D6 D5 D4 D3 D2 D1 D0 DASTS0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ EP0iDE DASTS1 ⎯ ⎯ ⎯ ⎯ ⎯ EP3DE EP2DE ⎯ TRG0 ⎯ ⎯ ⎯ ⎯ ⎯ EP0sRDFN EP0oRDFN EP0
PAGE 1286
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module IPRL ⎯ IPRL14 IPRL13 IPRL12 ⎯ IPRL10 IPRL9 IPRL8 INTC ⎯ IPRL6 IPRL5 IPRL4 ⎯ IPRL2 IPRL1 IPRL0 ⎯ IPRM14 IPRM13 IPRM12 ⎯ IPRM10 IPRM9 IPRM8 ⎯ IPRM6 IPRM5 IPRM4 ⎯ IPRM2 IPRM1 IPRM0 IPRM ⎯ IPRN14 IPRN13 IPRN12 ⎯ IPRN10 IPRN9 IPRN8 ⎯ IPRN6 IPRN5 IPRN4 ⎯ IPRN2 IPRN1 IPRN0 DTCERI DTCEI7 DTCEI6 DTCEI5 DTCEI4
PAGE 1287
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TIORL_6 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 TPU_6 TIER_6 TTGE ⎯ ⎯ TCIEV TGIED TGIEC TGIEB TGIEA TSR_6 ⎯ ⎯ ⎯ TCFV TGFD TGFC TGFB TGFA TCNT_6 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 TGRA_6 TGRB_6 TGRC_6 TGRD_6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit
PAGE 1288
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TGRA_8 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 TPU_8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TGRB_8 TCR_9 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_9 ⎯ ⎯ BFB BFA MD3 MD2 MD
PAGE 1289
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCR_11 ⎯ CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_11 TMDR_11 ⎯ ⎯ ⎯ ⎯ MD3 MD2 MD1 MD0 TIOR_11 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_11 TTGE ⎯ TCIEU TCIEV ⎯ ⎯ TGIEB TGIEA TSR_11 TCFD ⎯ TCFU TCFV ⎯ ⎯ TGFB TGFA TCNT_11 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 B
PAGE 1290
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ICCRA_1 ICE RCVD MST TRS CKS3 CKS2 CKS1 CKS0 IIC2_1 ICCRB_1 BBSY SCP SDAO ⎯ SCLO ⎯ IICRST ⎯ ICMR_1 ⎯ WAIT ⎯ ⎯ BCWP BC2 BC1 BC0 ICIER_1 TIE TEIE RIE NAKIE STIE ACKE ACKBR ACKBT ICSR_1 TDRE TEND RDRF NACKF STOP AL AAS ADZ SAR_1 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 ⎯ ICDRT_1 ICDRT7 ICDRT6 ICDRT5 ICDRT4
PAGE 1291
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SSTDR0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSU SSTDR1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSTDR2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSTDR3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSRDR0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSRDR1 Bit 7 Bit 6 Bit 5 Bit
PAGE 1292
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module EDDAR_3 Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 EXDMAC_3*7 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 31 Bit 30 Bit 29 Bit
PAGE 1293
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module IPRJ ⎯ IPRJ14 IPRJ13 IPRJ12 ⎯ IPRJ10 IPRJ9 IPRJ8 INT ⎯ IPRJ6 IPRJ5 IPRJ4 ⎯ IPRJ2 IPRJ1 IPRJ0 ⎯ IPRK14 IPRK13 IPRK12 ⎯ IPRK10 IPRK9 IPRK8 ⎯ IPRK6 IPRK5 IPRK4 ⎯ IPRK2 IPRK1 IPRK0 IPRK ITSR SSIER ISCRH ISCRL ITS15 ITS14 ITS13 ⎯ ⎯ ⎯ ⎯ ITS8 ITS7 ITS6 ITS5 ITS4 ITS3 ITS2 ITS1 ITS0 SSI15 SSI14 SSI13 SSI12
PAGE 1294
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PDPCR PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR PORT PEPCR PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR P3ODR ⎯ ⎯ P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR PAODR SMR_3* 4 C/A CHR PE O/E STOP MP CKS1 CKS0 SMR_3*5 GM BLK PE O/E
PAGE 1295
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TGRB_3 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 TPU_3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TGRC_3 TGRD_3 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 B
PAGE 1296
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ABWCR ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 BSC ASTCR AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 WTCRAH ⎯ W72 W71 W70 ⎯ W62 W61 W60 WTCRAL ⎯ W52 W51 W50 ⎯ W42 W41 W40 WTCRBH ⎯ W32 W31 W30 ⎯ W22 W21 W20 WTCRBL ⎯ W12 W11 W10 ⎯ W02 W01 W00 RDNCR RDN7 RDN6 RDN5 RDN4 RDN3 RDN2 RDN1 RDN0 CSACRH CSXH
PAGE 1297
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MAR_0BL Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 DMAC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOAR_0B ETCR_0B MAR_1AH MAR_1AL IOAR_1A ETCR_1A MAR_1BH MAR_1BL IOARV1B ETCR_1B DMAWER Bit 15 B
PAGE 1298
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module DMABCRH* 2 FAE1 FAE0 SAE1 SAE0 DTA1B DTA1A DTA0B DTA0A DMAC DMABCRH* 3 FAE1 FAE0 ⎯ ⎯ DTA1 ⎯ DTA0 ⎯ DMABCRL* 2 DTE1B DTE1A DTE0B DTE0A DTIE1B DTIE1A DTIE0B DTIE0A DMABCRL* 3 DTME1 DTE1 DTME0 DTE0 DTIE1B DTIE1A DTIE0B DTIE0A DTCERA DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTCERB DTCEB7 DTCEB6
PAGE 1299
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PODRL POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 PPG 6 NDRHH* NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 6 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 NDRHL* 6 ⎯ ⎯ ⎯ ⎯ NDR11 NDR10 NDR9 NDR8 NDRLL* 6 ⎯ ⎯ ⎯ ⎯ NDR3 NDR2 NDR1 NDR0 PORT1 P17 P16 P15 P14 P13 P12 P11 P10 PORT2 P27 P26 P25 ⎯ ⎯ ⎯ ⎯ P20
PAGE 1300
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PGDR ⎯ PG6DR PG5DR PG4DR PG3DR PG2DR PG1DR PG0DR PORT PORTH ⎯ ⎯ ⎯ ⎯ PH3 PH2 PH1 PH0 PORTJ ⎯ ⎯ ⎯ ⎯ ⎯ PJ2 PJ1 PJ0 PHDR ⎯ ⎯ ⎯ ⎯ PH3DR PH2DR PH1DR PH0DR PJDR ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PJ1DR PJ0DR PHDDR ⎯ ⎯ ⎯ ⎯ PH3DDR PH2DDR PH1DDR PH0DDR ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PJ1DDR PJ0DDR 4 C/A CHR PE O/E STOP MP CKS1 CKS0 SMR_0
PAGE 1301
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SSR_2* TDRE RDRF ORER ERS PER TEND MPB MPBT SCI_2, Smart RDR_2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCMR_2 BCP2 ⎯ ⎯ ⎯ SDIR SINV ⎯ SMIF ADDRA_0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
PAGE 1302
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCNT_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR_0 TCNT_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR_1 TCCR0 ⎯ ⎯ ⎯ ⎯ TMRIS ⎯ ICKS1 ICKS0 8-bit TCCR1 ⎯ ⎯ ⎯ ⎯ TMRIS ⎯ ICKS1 ICKS0 TCSR OVF WT/IT TME ⎯ ⎯ CKS2 CKS1 CKS0 TCNT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RSTCSR WOVF
PAGE 1303
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TSR_1 TCFD ⎯ TCFU TCFV ⎯ ⎯ TGFB TGFA TPU_1 TCNT_1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 TGRA_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
PAGE 1304
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers 25.
PAGE 1305
H8S/2456, H8S/2456R, H8S/2454 Group Register Section 25 List of Registers High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module EPSTL1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized USB STLSR1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized DMAR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized CVR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized CTLR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized EPIR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TRNTR
PAGE 1306
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module TSR_6 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TPU_6 TCNT_6 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TGRA_6 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TGRB_6 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TGRC_6 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TGRD_6 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initiali
PAGE 1307
H8S/2456, H8S/2456R, H8S/2454 Group Register Section 25 List of Registers High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module TGRD_9 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TPU_9 TCR_10 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TPU_10 TMDR_10 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TIOR_10 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TIER_10 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TSR_10 Initialized ⎯ ⎯ ⎯ ⎯ ⎯
PAGE 1308
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module ICCRA_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized IIC2_0 ICCRB_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized ICMR_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized ICIER_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized ICSR_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized SAR_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Init
PAGE 1309
H8S/2456, H8S/2456R, H8S/2454 Group Register Section 25 List of Registers High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module SEMR_2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized SCI_2 SSCRH Initialized ⎯ ⎯ ⎯ Initialized Initialized Initialized Initialized SSU SSCRL Initialized ⎯ ⎯ ⎯ Initialized Initialized Initialized Initialized SSMR Initialized ⎯ ⎯ ⎯ Initialized Initialized Initialized Initialized SSER Init
PAGE 1310
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module IPRH Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized INT IPRI Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized IPRJ Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized IPRK Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized ITSR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized SSIER Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized ISCRH
PAGE 1311
H8S/2456, H8S/2456R, H8S/2454 Group Register Section 25 List of Registers High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module SMR_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized SCI_3 BRR_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized SCR_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TDR_3 Initialized ⎯ ⎯ ⎯ Initialized Initialized Initialized Initialized SSR_3 Initialized ⎯ ⎯ ⎯ Initialized Initialized Initialized Initia
PAGE 1312
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module TGRB_4 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TPU_4 TCR_5 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TPU_5 TMDR_5 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TIOR_5 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TIER_5 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TSR_5 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ In
PAGE 1313
H8S/2456, H8S/2456R, H8S/2454 Group Register Section 25 List of Registers High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module MAR_0AH Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized DMAC MAR_0AL Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized IOAR_0A Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized ETCR_0A Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized MAR_0BH Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized MAR_0BL Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ In
PAGE 1314
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module DTVECR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized DTC INTCR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized INT IER Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized ISR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized SBYCR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized SCKCR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized
PAGE 1315
H8S/2456, H8S/2456R, H8S/2454 Group Register Section 25 List of Registers High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module PORTB ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PORT PORTC ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PORTD ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PORTE ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PORTF ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PORTG ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ P1DR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized P2DR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized P3DR Initialized ⎯
PAGE 1316
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module SMR_1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized SCI_1 BRR_1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized SCR_1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TDR_1 Initialized ⎯ ⎯ ⎯ Initialized Initialized Initialized Initialized SSR_1 Initialized ⎯ ⎯ ⎯ Initialized Initialized Initialized Initia
PAGE 1317
H8S/2456, H8S/2456R, H8S/2454 Group Register Section 25 List of Registers High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module TCR_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TMR_0 TCR_1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TMR_1 TCSR_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TCSR_1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TCORA_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TCORA_1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
PAGE 1318
H8S/2456, H8S/2456R, H8S/2454 Group Section 25 List of Registers Register High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module TMDR_1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TPU_0 TIOR_1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TIER_1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TSR_1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TCNT_1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TGRA_1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initiali
PAGE 1319
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics Section 26 Electrical Characteristics 26.1 Electrical Characteristics for H8S/2456 Group and H8S/2456R Group 26.1.1 Absolute Maximum Ratings Table 26.1 lists the absolute maximum ratings. Table 26.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC −0.3 to +4.3 V PLLVCC DrVCC Input voltage (except ports 4, 9, 2, P32 to P35, P50, P51, and PJ0 to PJ2) Vin −0.3 to VCC +0.
PAGE 1320
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics 26.1.2 DC Characteristics Table 26.2 DC Characteristics (1) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1 Typ. Max. Test Unit Conditions ⎯ ⎯ V ⎯ VCC × 0.7 V ⎯ ⎯ V VCC × 0.9 ⎯ VCC +0.3 V RES, NMI, FWE VCC × 0.9 ⎯ VCC +0.3 V EXTAL VCC × 0.7 ⎯ VCC +0.3 V P14 to P17*5, P25*5, P26*5, port 3*3, P50 to P53*3, 3 3 ports 6* and 8* , 3 * ports A to J 2.
PAGE 1321
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics Item Symbol Min. Typ. Max. Test Unit Conditions Output high All output pins voltage VOH VCC − 0.3 ⎯ ⎯ V IOH = −200 μA VCC − 0.5 ⎯ ⎯ V IOH = −1 mA VCC − 0.8 ⎯ ⎯ V IOH = −2 mA ⎯ ⎯ 0.4 V IOL = 4.0 mA ⎯ ⎯ 0.4 V IOL = 8.0 mA ⎯ ⎯ 10.0 μA STBY, NMI, MD2 to MD0 ⎯ ⎯ 1.0 μA Vin = 0.5 to VCC −0.5 V Port 4, Port 9 ⎯ ⎯ 1.
PAGE 1322
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics Table 26.3 DC Characteristics (2) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1 Item Symbol Min. Typ. Max. Test Unit Conditions Three-state leakage current (off state) Ports 1 to 3, P50 to P53, ports 6 and 8, ports A to I | ITSI | ⎯ ⎯ 1.0 μA Vin = 0.5 to VCC −0.5 V Input pull-up MOS current Ports A to E −Ip 10 ⎯ 300 μA VCC = 3.0 to 3.
PAGE 1323
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics 3. The values are for VRAM ≤ VCC < 3.0 V, VIHmin = VCC × 0.9, and VILmax = 0.3 V. 4. ICC depends on VCC and f as follows: ICCmax = 5.2 (mA) + 1.66 (mA/(MHz)) × f (normal operation) ICCmax = 2.6 (mA) + 1.28 (mA/(MHz)) × f (sleep mode) 5. Applied when RES is low at power-on. Table 26.4 Permissible Output Currents Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V* Item Symbol Min. Typ.
PAGE 1324
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics 26.1.3 AC Characteristics The following shows the timings of the clock, control signals, bus, DMAC, EXDMAC, and onchip peripheral functions. For the AC characteristic test conditions, see figure 26.1. (1) Clock Timing Table 26.5 Clock Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Symbol Min. Max.
PAGE 1325
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics 3V RL C=50pF: Ports A to J (except for PH1 when SDRAMφ is in use.) C=30pF: Ports 1 to 3, P50 to P52, Port6, Port8, and PH1 when SDRAMφ is in use. LSI output pin RL=2.4kΩ RH=12kΩ I/O timing test level 1.5V: (Vcc=3.0 to 3.6V) C RH Note: * Not supported by the H8S/2456R Group. Figure 26.1 Output Load Circuit (2) Control Signal Timing Table 26.6 Control Signal Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.
PAGE 1326
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics (3) Bus Timing Table 26.7 Bus Timing (1) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Symbol Min. Max. Unit Test Conditions Address delay time tAD Address setup time 1 tAS1 ⎯ 20 ns 0.5 × tcyc −13 ⎯ ns Figures 26.8 to 26.23, 26.29, and 26.30 Address setup time 2 tAS2 1.0 × tcyc −13 ⎯ ns Address setup time 3 tAS3 1.
PAGE 1327
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics Item Symbol Min. Max. Unit Test Conditions Counter address read data access time 2 tAA2 ⎯ 1.5 × tcyc − 25 ns Counter address read data access time 3 tAA3 ⎯ 2.0 × tcyc − 25 ns Figures 26.8 to 26.23, 26.29, and 26.30 Counter address read data access time 4 tAA4 ⎯ 2.5 × tcyc − 25 ns Counter address read data access time 5 tAA5 ⎯ 3.0 × tcyc − 25 ns Counter address read data access time 6 tAA6 ⎯ 4.
PAGE 1328
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics Item Symbol Min. Max. Unit Test Conditions Read command hold time tRCH 0.5 × tcyc −10 ⎯ ns CAS delay time 1 tCASD1 ⎯ 15 ns CAS delay time 2 Figures 26.8 to 26.23, 26.29, and 26.30 tCASD2 ⎯ 15 ns CAS setup time 1 tCSR1 0.5 × tcyc −10 ⎯ ns CAS setup time 2 tCSR2 1.5 × tcyc −10 ⎯ ns CAS pulse width 1 tCASW1 1.0 × tcyc −20 ⎯ ns CAS pulse width 2 tCASW2 1.
PAGE 1329
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics Notes: 1. tOED1, and tOED2 correspond to the OE-A and RD, and, tOED1B, and tOED2B correspond to the OE-B. 2. Supported only by the H8S/2456R Group. 3. tCKED corresponds to the CKE-A, tCKEDB corresponds to the CKE-B. (4) DMAC and EXDMAC Timing Table 26.9 DMAC and EXDMAC Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Symbol Min. Max.
PAGE 1330
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics (5) Timing of On-Chip Peripheral Modules Table 26.10 Timing of On-Chip Peripheral Modules Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Symbol Min. Max. Unit Test Conditions 40 ns Figure 26.39 tPWD ⎯ Input data setup time tPRS 25 ⎯ ns Input data hold time tPRH 25 ⎯ ns PPG Pulse output delay time tPOD ⎯ 40 ns Figure 26.
PAGE 1331
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics Item Symbol Min. Max. Unit Test Conditions A/D converter Trigger input setup time tTRGS 30 ⎯ ns Figure 26.49 IIC2 SCL input cycle time tSCL 12 tcyc +600 ⎯ ns Figure 26.
PAGE 1332
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics Item SCS hold time SSU* Master Symbol Min. Max. Unit Test Conditions tLAG 2.5 ⎯ tcyc 2.5 ⎯ Figures 26.51 to 26.54 ⎯ 40 ⎯ 40 −5 ⎯ 0 ⎯ 2.5 ⎯ 2.5 ⎯ Slave Note * 26.1.4 Data output delay time Master Data output hold time Master tOD Slave tOH Slave ns ns Continuous Master transmit delay time Slave tTD tcyc Slave access time tSA ⎯ 1 tcyc Slave out release time tREL ⎯ 1 tcyc Figures 26.
PAGE 1333
H8S/2456, H8S/2456R, H8S/2454 Group 26.1.5 Section 26 Electrical Characteristics D/A Conversion Characteristics Table 26.12 D/A Conversion Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Min. Typ. Max. Unit Resolution 8 8 8 Bit Conversion time ⎯ ⎯ 10 μs Absolute accuracy ⎯ ±2.0 ±3.0 LSB 2 MΩ resistive load ⎯ ⎯ ±2.0 LSB 4 MΩ resistive load 26.1.
PAGE 1334
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics Table 26.14 USB PLL Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6, Vref = 3.0 V to AVCC, VSS = AVSS = 0V, EXTAL = 8 to 16 MHz Item Symbol Min Max Unit Test Conditions PLL for USB: oscillation stabilization time tUSOSC 1 ⎯ ms Figure 26.38 26.1.7 Flash Memory Characteristics Table 26.15 Flash Memory Characteristics Conditions: VCC = 3.0 to 3.6V, AVCC = 3.0 to 3.6V, Vref = 3.
PAGE 1335
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics *1. Determination of the number of times for programming/erasure operations. Number of times programming/erasure is performed in each block. When the number of times for programming/erasure operations is n (n = 100), data can be erased n times in each block.
PAGE 1336
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics 26.2 Electrical Characteristics for H8S/2454 Group 26.2.1 Absolute Maximum Ratings Table 26.16 lists the absolute maximum ratings. Table 26.16 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC −0.3 to +4.3 V PLLVCC DrVCC Input voltage (except ports 4, 9, 2, P32 to P35, P50, P51, P81, and P83) Vin −0.3 to VCC +0.3 V Input voltage (ports 2, P32 to P35, P50, P51, P81, and P83) Vin −0.3 to +6.
PAGE 1337
H8S/2456, H8S/2456R, H8S/2454 Group 26.2.2 Section 26 Electrical Characteristics DC Characteristics Table 26.17 DC Characteristics (1) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1 Typ. Max. Test Unit Conditions VCC × 0.2 ⎯ ⎯ V ⎯ ⎯ VCC × 0.7 V VCC × 0.07 ⎯ ⎯ V VCC × 0.9 ⎯ VCC +0.3 V VCC × 0.7 ⎯ VCC +0.3 V P10 to P11* , P14 to P17*5, 5 5 P25* , P26* , 3 port 3* , P50 to P53*3, 3 port 8* , ports A to G*3 2.2 ⎯ VCC +0.
PAGE 1338
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics Item Symbol Min. Typ. Max. Test Unit Conditions Output high All output pins voltage VOH VCC − 0.3 ⎯ ⎯ V IOH = −200 μA VCC − 0.5 ⎯ ⎯ V IOH = −1 mA VCC − 0.8 ⎯ ⎯ V IOH = −2 mA ⎯ ⎯ 0.4 V IOL = 4.0 mA ⎯ ⎯ 0.4 V IOL = 8.0 mA ⎯ ⎯ 10.0 μA STBY, NMI, MD2 to MD0 ⎯ ⎯ 1.0 μA Vin = 0.5 to VCC −0.5 V Port 4, Port 9 ⎯ ⎯ 1.
PAGE 1339
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics Table 26.18 DC Characteristics (2) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1 Item Symbol Min. Typ. Max. Unit Test Conditions Three-state leakage current (off state) Ports 1 to 3, P50 to P53, Ports 8, Ports A to G | ITSI | ⎯ ⎯ 1.0 μA Vin = 0.5 to VCC −0.5 V Input pull-up MOS current Ports A to E −Ip 10 ⎯ 300 μA VCC = 3.0 to 3.
PAGE 1340
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics 3. The values are for VRAM ≤ VCC < 3.0 V, VIHmin = VCC × 0.9, and VILmax = 0.3 V. 4. ICC depends on VCC and f as follows: ICCmax = 5.2 (mA) + 1.66 (mA/(MHz)) × f (normal operation) ICCmax = 2.6 (mA) + 1.28 (mA/(MHz)) × f (sleep mode) 5. Applied when RES is low at power-on. Table 26.19 Permissible Output Currents Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V* Item Symbol Min. Typ.
PAGE 1341
H8S/2456, H8S/2456R, H8S/2454 Group 26.2.3 Section 26 Electrical Characteristics AC Characteristics The following shows the timings of the clock, control signals, bus, DMAC, and on-chip peripheral functions. For the AC characteristic test conditions, see figure 26.2. (1) Clock Timing Table 26.20 Clock Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Symbol Min. Max. Unit Test Conditions Clock cycle time tcyc 30.
PAGE 1342
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics 3V RL C=50pF: Ports A to G C=30pF: Ports 1 to 3, P50 to P53, and Port8 RL=2.4kΩ RH=12kΩ I/O timing test level1.5V: (Vcc=3.0 to 3.6V) LSI output pin C RH Figure 26.2 Output Load Circuit (2) Control Signal Timing Table 26.21 Control Signal Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Symbol Min. Max.
PAGE 1343
H8S/2456, H8S/2456R, H8S/2454 Group (3) Section 26 Electrical Characteristics Bus Timing Table 26.22 Bus Timing (1) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Symbol Min. Max. Unit Test Conditions Address delay time tAD ⎯ 20 ns Address setup time 1 tAS1 0.5 × tcyc −13 ⎯ ns Figures 26.8 to 26.23, 26.29, and 26.30 Address setup time 2 tAS2 1.0 × tcyc −13 ⎯ ns Address setup time 3 tAS3 1.
PAGE 1344
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics Item Min. Max. Unit Test Conditions Counter address read data access time 4 tAA4 Symbol ⎯ 2.5 × tcyc − 25 ns Counter address read data access time 5 tAA5 ⎯ 3.0 × tcyc − 25 ns Figures 26.8 to 26.23, 26.29, and 26.30 Counter address read data access time 6 tAA6 ⎯ 4.0 × tcyc − 25 ns Multiplex address delay time 6 TMAD ⎯ 20 ns Multiplex address setup time 1 TMAS1 0.
PAGE 1345
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics Table 26.22 Bus Timing (2) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Symbol Min. Max. Unit Test Conditions WR delay time 1 tWRD1 ⎯ 15 ns WR delay time 2 tWRD2 ⎯ 15 ns WR pulse width 1 tWSW1 1.0 × tcyc −13 ⎯ Figures 26.8 to 26.23, 26.29, and 26.30 ns WR pulse width 2 tWSW2 1.
PAGE 1346
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics Item Symbol Min. Max. Unit Test Conditions OE delay time 2* tOED2 ⎯ 15 ns Figures 26.8 to 26.23, 26.29, and 26.30 tOED2B ⎯ 19 ns Precharge time 1 tPCH1 1.0 × tcyc −20 ⎯ ns Precharge time 2 tPCH2 1.5 × tcyc −20 ⎯ ns Self-refresh precharge time 1 tRPS1 2.5 × tcyc −20 ⎯ ns Self-refresh precharge time 2 tRPS2 3.
PAGE 1347
H8S/2456, H8S/2456R, H8S/2454 Group (5) Section 26 Electrical Characteristics Timing of On-Chip Peripheral Modules Table 26.24 Timing of On-Chip Peripheral Modules Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Symbol Min. Max. Unit Test Conditions Figure 26.39 tPWD ⎯ 40 ns Input data setup time tPRS 25 ⎯ ns Input data hold time tPRH 25 ⎯ ns PPG Pulse output delay time tPOD ⎯ 40 ns Figure 26.
PAGE 1348
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics Item Symbol Min. Max. Unit Test Conditions A/D converter Trigger input setup time tTRGS 30 ⎯ ns Figure 26.49 IIC2 SCL input cycle time tSCL 12 tcyc +600 ⎯ ns Figure 26.
PAGE 1349
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics Item SCS hold time SSU* Master Symbol Min. Max. Unit Test Conditions tLAG 2.5 ⎯ tcyc 2.5 ⎯ Figures 26.51 to 26.54 ⎯ 40 ⎯ 40 Slave Note * 26.2.4 Data output delay time Master Data output hold time Master tOD Slave tOH Slave 0 ⎯ 0 ⎯ 2.5 ⎯ 2.5 ⎯ ns ns Continuous Master transmit delay time Slave tTD tcyc Slave access time tSA ⎯ 1 tcyc Slave out release time tREL ⎯ 1 tcyc Figures 26.
PAGE 1350
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics 26.2.5 D/A Conversion Characteristics Table 26.26 D/A Conversion Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Min. Typ. Max. Unit Resolution 8 8 8 Bit Conversion time ⎯ ⎯ 10 μs Absolute accuracy ⎯ ±2.0 ±3.0 LSB 2 MΩ resistive load ⎯ ⎯ ±2.0 LSB 4 MΩ resistive load 26.2.
PAGE 1351
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics Table 26.28 USB PLL Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6, Vref = 3.0 V to AVCC, VSS = AVSS = 0V, EXTAL = 8 to 16 MHz Item Symbol Min Max Unit Test Conditions PLL for USB: oscillation stabilization time tUSOSC 1 ⎯ ms Figure 26.38 26.2.7 Flash Memory Characteristics Table 26.29 Flash Memory Characteristics Conditions: VCC = 3.0 to 3.6V, AVCC = 3.0 to 3.6V, Vref = 3.
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Section 26 Electrical Characteristics H8S/2456, H8S/2456R, H8S/2454 Group *1. Determination of the number of times the programming/erase operation. Number of times the programming/erase performed in each block. When the number of times the programming/erase is n times (n = 100), data can be erased n times in each block.
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H8S/2456, H8S/2456R, H8S/2454 Group 26.3 Timing Charts 26.3.1 Clock Timing Section 26 Electrical Characteristics The clock timings are shown below. tcyc tCH tCf φ tCL tCr Figure 26.3 System Clock Timing tcyc tCH tCf φ tCr tCL tcdif tsdcf tsdcr SDRAMφ tSDCH tSDCL Figure 26.4 SDRAMφ Timing R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics EXTAL tDEXT tDEXT VCC STBY tOSC1 tOSC1 RES φ Figure 26.5 (1) Oscillation Settling Timing Oscillator φ NMI NMIEG SSBY NMI exception handling NMI exception handling NMIEG = 1 SSBY = 1 Software standby mode (power-down state) Oscillation stabilization time tOSC2 SLEEP instruction Figure 26.5 (2) Oscillation Settling Timing Page 1324 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group 26.3.2 Section 26 Electrical Characteristics Control Signal Timing The control signal timings are shown below. φ tRESS tRESS RES tRESW Figure 26.6 Reset Input Timing φ tNMIS tNMIH NMI tNMIW tIRQW IRQi (i = 0 to 15)* tIRQS tIRQH IRQ (edge input) tIRQS IRQ (level input) Note: * SSIER setting is necessary to clear software standby mode. Figure 26.7 Interrupt Input Timing R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics 26.3.3 Bus Timing The bus timings are shown below. T2 T1 φ tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD tASD tAH1 AS tAS1 tRSD1 tRSD1 RD Read (RDNn = 1) tRDS1 tRDH1 tAC5 tAA2 D15 to D0 tAS1 tRSD1 tRSD2 RD Read (RDNn = 0) tAC2 tRDS2 tRDH2 tAA3 D15 to D0 tAS1 tWRD2 tWRD2 tAH1 HWR, LWR tWDD Write tWSW1 tWDH1 D15 to D0 tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Figure 26.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics T1 T3 T2 φ tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD tASD tAH1 AS tAS1 tRSD1 tRSD1 RD Read (RDNn = 1) tRDS1 tRDH1 tAC6 tAA4 D15 to D0 tAS1 tRSD1 tRSD2 RD Read (RDNn = 0) tRDS2 tAC4 tRDH2 tAA5 D15 to D0 tAS2 tWRD2 tAH1 tWRD1 HWR, LWR tWDS1 tWDD Write tWSW2 tWDH1 D15 to D0 tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Figure 26.9 Basic Bus Timing: Three-State Access R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics T1 T2 Tw tWTS tWTH tWTS tWTH T3 φ A23 to A0 CS7 to CS0 AS RD Read (RDNn = 1) D15 to D0 RD Read (RDNn = 0) D15 to D0 HWR, LWR Write D15 to D0 WAIT Figure 26.10 Basic Bus Timing: Three-State Access, One Wait Page 1328 of 1408 R01UH0309EJ0500 Rev. 5.
PAGE 1359
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics T1 Th T2 Tt φ tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tAH1 tASD tASD AS tAS3 tAH3 tRSD1 tRSD1 RD Read (RDNn = 1) tAC5 tRDS1 tRDH1 tRSD1 tRSD2 D15 to D0 tAS3 tAH2 RD Read (RDNn = 0) tAC2 tRDS2 tRDH2 D15 to D0 tAS3 tWRD2 tWRD2 tAH3 HWR, LWR tWDD Write tWDS2 tWSW1 tWDH3 D15 to D0 tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Figure 26.
PAGE 1360
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics Th T1 T2 T3 Tt φ tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD tAH1 tASD AS tAS3 tRSD1 tAH3 tRSD1 RD Read (RDNn = 1) tRDS1 tRDH1 tAC6 D15 to D0 tAS3 tAH2 tRSD2 tRSD1 RD Read (RDNn = 0) tRDS2 tRDH2 tAC4 D15 to D0 tAS4 tAH3 tWRD1 HWR, LWR tWDD Write tWRD2 tWDS3 tWSW2 tWDH3 D15 to D0 tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Figure 26.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics T1 T2 T1 T1 φ A23 to A6, A0 tAD A5 to A1 CS1, CS0 AS tRSD2 RD tAA1 tRDS2 tRDH2 Read D15 to D0 HWR, LWR Figure 26.13 Burst ROM Access Timing: One-State Burst Access R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics T1 T2 T3 T1 T2 φ A23 to A6, A0 tAD A5 to A1 CS1, CS0 tAH1 tAS1 tASD AS tASD tRSD2 RD Read tAA3 tRDS2 tRDH2 D15 to D0 HWR, LWR Figure 26.14 Burst ROM Access Timing: Two-State Burst Access Page 1332 of 1408 R01UH0309EJ0500 Rev. 5.
PAGE 1363
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics Tr Tp Tc1 Tc2 φ tAD tAD A23 to A0 tAS3 RAS5 to RAS2 tCSD3 tAH1 tCSD2 tAS2 tPCH2 tAH2 tCASD1 tCASD1 UCAS tCASW1 LCAS tOED1/ tOED1B tOED1/ tOED1B tAC1 OE, RD Read HWR tAA3 tRDS2 tRDH2 tAC4 D15 to D0 OE, RD tWRD2 Write tWCS1 tWCH1 tWRD2 HWR tWDD tWDS1 tWDH2 D15 to D0 AS tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Note: DACK and EDACK timing: when DDS = 0 and EDDS = 0 RAS timing: when RAST
PAGE 1364
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics Tp Tr Tc1 Tcw Tcwp Tc2 φ A23 to A0 RAS5 to RAS2 UCAS, LCAS OE, RD Read HWR D15 to D0 UCAS, LCAS OE, RD Write HWR D15 to D0 AS tWTS tWTH tWTS tWTH WAIT DACK0, DACK1 EDACK2, EDACK3 Note: DACK and EDACK timing: when DDS = 0 and EDDS = 0 RAS timing: when RAST = 0 Tcw: Wait cycle inserted by programmable wait function Tcwp: Wait cycle inserted by pin wait function Figure 26.
PAGE 1365
H8S/2456, H8S/2456R, H8S/2454 Group Tp Section 26 Electrical Characteristics Tr Tc1 Tc2 Tc1 Tc2 φ A23 to A0 RAS5 to RAS2 tCPW1 UCAS LCAS OE, RD Read HWR tAC3 D15 to D0 OE, RD Write tRCH HWR tRCS1 D15 to D0 AS tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Note: DACK and EDACK timing: when DDS = 0 and EDDS = 0 RAS timing: when RAST = 0 Figure 26.17 DRAM Access Timing: Two-State Burst Access R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics Tp Tr Tc1 Tc3 Tc2 φ tAD tAD A23 to A0 tAS2 RAS5 to RAS2 tCSD3 tAH2 tCSD1 tPCH1 tAS3 tAH3 tCASD1 tCASD2 UCAS tCASW2 LCAS tOED2/ tOED2B tOED1/ tOED1B tAC2 OE, RD Read HWR tAA5 tRDS2 tRDH2 tAC7 D15 to D0 OE, RD Write tWRD2 tWCS2 tWCH2 tWRD2 HWR tWDD tWDS2 tWDH3 D15 to D0 AS tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Note: DACK and EDACK timing: when DDS = 0 and EDDS = 0 RAS timin
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H8S/2456, H8S/2456R, H8S/2454 Group Tp Section 26 Electrical Characteristics Tr Tc1 Tc2 Tc3 Tc1 Tc2 Tc3 φ A23 to A0 RAS5 to RAS0 tCPW2 UCAS LCAS OE, RD Read HWR tAC8 D15 to D0 OE, RD Write tRCH HWR tRCS2 D15 to D0 AS DACK0, DACK1 EDACK2, EDACK3 Note: DACK and EDACK timing: when DDS = 1 and EDDS = 1 RAS timing: when RAST = 1 Figure 26.19 DRAM Access Timing: Three-State Burst Access R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics TRp TRc1 TRr TRc2 φ tCSD1 tCSD2 RAS5 to RAS2 tCSR1 tCASD1 tCASD1 UCAS, LCAS OE Figure 26.20 CAS-Before-RAS Refresh Timing TRp TRrw TRr TRc1 TRcw TRc2 φ tCSD1 tCSD2 RAS5 to RAS2 UCAS, LCAS tCSR2 tCASD1 tCASD1 OE Figure 26.21 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion) Page 1338 of 1408 R01UH0309EJ0500 Rev. 5.
PAGE 1369
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics Self-refresh TRp TRr TRc TRc DRAM access TRp Tp Tr φ tCSD2 tCSD2 RAS5 to RAS2 tRPS2 tCASD1 tCASD1 UCAS, LCAS OE Figure 26.22 Self-Refresh Timing (Return from Software Standby Mode: RAST = 0) Self-refresh TRp TRr TRc TRc TRp DRAM access Tp Tr φ tCSD2 RAS5 to RAS2 tCASD1 tCSD2 tRPS1 tCASD1 UCAS, LCAS OE Figure 26.23 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1) R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics φ tBREQS tBREQS BREQ tBACD tBACD BACK tBZD tBZD A23 to A0 CS7 to CS0 (RAS5 to RAS2) D15 to D0 AS, RD HWR, LWR UCAS, LCAS, OE Figure 26.24 External Bus Release Timing φ BACK tBRQOD tBRQOD BREQO Figure 26.25 External Bus Request Output Timing Page 1340 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics Tr Tp Tc1 Tw Tc2 φ SDRAMφ tAD2 Address bus Precharge-sel RAS tCSD4 tCSD4 tCSD4 CAS Read tCSD4 tCSD4 tCSD4 WE CKE tDQMD tDQMD High DQMU, DQML tRDS3 tRDH3 Data bus tCSD4 tCSD4 RAS tCSD4 CAS tCSD4 tCSD4 tCSD4 WE tCSD4 tCSD4 Write CKE High tDQMD DQMU, DQML tDQMD tWDD Data bus tWDH4 Figure 26.26 Synchronous DRAM Basic Access Timing (CAS Latency 2) R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics TRp TRr Software standby TRr2 φ SDRAMφ Address bus Precharge-sel RAS CAS WE tCKED/ tCKEDB CKE tCKED/ tCKEDB Figure 26.27 Synchronous DRAM Self-Refresh Timing Page 1342 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Tp Section 26 Electrical Characteristics Tr Tc1 Tc2 TRr Ttp2 φ SDRAMφ Address bus Precharge-sel RAS CAS WE tCKED/ tCKEDB tCKED/ tCKEDB CKE DQMU, DQML Data bus DACK or EDACK Figure 26.28 Read Data: Two-State Expansion (CAS Latency 2) R01UH0309EJ0500 Rev. 5.
PAGE 1374
Section 26 Electrical Characteristics 26.3.4 H8S/2456, H8S/2456R, H8S/2454 Group DMAC and EXDMAC Timing The DMAC and EXDMAC timings are shown below. Page 1344 of 1408 R01UH0309EJ0500 Rev. 5.
PAGE 1375
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics Tma1 Tma2 T1 T2 φ tAD A23 to A0 tCSD1 CS7, CS6 tAHD AH tRSD1 tRSD2 RD tAC2 Read (RDNn=0) tAA6 tMAD tMAS1 tMAH tRDS2 A15 to A0 AD15 to AD0 tRDH2 D15 toD0 tWRD2 tWRD2 HWR, LWR Write tWSW tMAD AD15 to AD0 tWDD A15 to A0 tWDH1 D15 toD0 tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Figure 26.29 Multiplexed Bus Timing: Data Two-State Access R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics Tma1 Tmaw Tma2 T1 T2 Tw T3 φ tAD A23 to A0 tCSD1 CS7, CS6 tAHD AH tRSD1 tRSD2 RD Read (RDNn=0) tMAD tMAS2 AD15 to AD0 tRDS2 tRDH2 tMAH A15 to A0 D15 to D0 tWRD1 tWRD2 HWR, LWR Write tWDD tWDS1 tMAD AD15 to AD0 tWDH1 D15 to D0 A15 to A0 tWTS tWTH tWTS tWTH WAIT Figure 26.30 Multiplexed Bus Timing: Data Three-State Access, One Wait (with Address Wait: When ADDEX = 1) Page 1346 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics T1 T2 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK0 to EDACK3 Figure 26.31 DMAC and EXDMAC Single Address Transfer Timing: Two-State Access R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics T1 T2 T3 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Figure 26.32 DMAC and EXDMAC Single Address Transfer Timing: Three-State Access Page 1348 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics T1 T2 or T3 φ tTED tTED tETED tETED TEND0, TEND1 ETEND2, ETEND3 Figure 26.33 DMAC and EXDMAC, TEND/ETEND Output Timing φ tDRQS tDRQH DREQ0, DREQ1 tEDRQS tEDRQH EDREQ2, EDREQ3 Figure 26.34 DMAC and EXDMAC, DREQ/EDREQ Input Timing φ tEDRKD tEDRKD EDRAK2, EDRAK3 Figure 26.35 EXDMAC, EDRAK Output Timing R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics 26.3.5 USB Characteristics The following figures describe USB characteristics. Rise Time USD+, USD- VCRS 90% Fall Time 90% 10% Differential Data Liness 10% tR tF Figure 26.36 Data Signal Timing Rs=27Ω USD+ Test Point CL=50pF Rs=27Ω USD- Test Point CL=50pF Figure 26.
PAGE 1381
H8S/2456, H8S/2456R, H8S/2454 Group 26.3.6 Section 26 Electrical Characteristics Timing of On-Chip Peripheral Modules The on-chip peripheral module timings are shown below. T1 T2 φ tPRS tPRH Ports 1 to 6, 8, 9, A to J (read) tPWD Ports 1 to 3, 6, 8, P53 to P50, ports A to J (write) Figure 26.39 I/O Port Input/Output Timing φ tPOD PO15 to PO0 Figure 26.40 PPG Output Timing R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics φ tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA11, TIOCB0 to TIOCB11, TIOCC0, TIOCC3, TIOCC6, TIOCC9, TIOCD0, TIOCD3, TIOCD6, and TIOCD9 Figure 26.41 TPU Input/Output Timing φ tTCKS tTCKS TCLKA to TCLKH tTCKWL tTCKWH Figure 26.42 TPU Clock Input Timing Page 1352 of 1408 R01UH0309EJ0500 Rev. 5.
PAGE 1383
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics φ tTMOD TMO0, TMO1 Figure 26.43 8-Bit Timer Output Timing φ tTMCS tTMCS TMCI0, TMCI1 tTMCWL tTMCWH Figure 26.44 8-Bit Timer Clock Input Timing φ tTMRS TMRI0, TMRI1 Figure 26.45 8-Bit Timer Reset Input Timing R01UH0309EJ0500 Rev. 5.
PAGE 1384
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics φ tWOVD tWOVD WDTOVF Figure 26.46 WDT Output Timing tSCKW tSCKr tSCKf SCK0 to SCK4 tScyc Figure 26.47 SCK Clock Input Timing SCK0 to SCK4 tTXD TxD0 to TxD4 (transmit data) tRXS tRXH RxD0 to RxD4 (receive data) Figure 26.48 SCI Input/Output Timing: Synchronous Mode φ tTRGS ADTRG0, ADTRG1 Figure 26.49 A/D Converter External Trigger Input Timing Page 1354 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics VIH SDA0 to SDA1 VIL tBUF tSCLH tSTAH SCL0 to SCL1 P* S* tSf tSTOS Sr* tSCLL tSr P* tSDAS tSCL Note: tSP tSTAS tSDAH S, P, and Sr represent the following conditions: S: Start condition P: Stop condition Sr: Retransmit start condition Figure 26.
PAGE 1386
H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics SCS (output) tTD tFALL tHI tLEAD tRISE tLAG SSCK (output) CPOS = 1 tLO tHI SSCK (output) CPOS = 0 tLO tSUcyc SSO (output) tOH tOD SSI (input) tSU tH Figure 26.52 SSU Timing (Master, CPHS = 0) SCS (input) tLEAD tFALL tHI tRISE tLAG tTD SSCK (input) CPOS = 1 tLO tHI SSCK (input) CPOS = 0 tLO tSUcyc SSO (input) tSU tH tREL SSI (output) tSA tOH tOD Figure 26.
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H8S/2456, H8S/2456R, H8S/2454 Group Section 26 Electrical Characteristics SCS (input) tLEAD tFALL tHI tRISE tLAG tTD SSCK (input) CPOS = 1 tLO tHI SSCK (input) CPOS = 0 tSUcyc tLO SSO (input) tSU tH tREL SSI (output) tSA tOH tOD Figure 26.54 SSU Timing (Slave, CPHS = 0) R01UH0309EJ0500 Rev. 5.
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Section 26 Electrical Characteristics Page 1358 of 1408 H8S/2456, H8S/2456R, H8S/2454 Group R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group Appendix Appendix A. Port States in Each Processing State Table A.
PAGE 1390
H8S/2456, H8S/2456R, H8S/2454 Group Appendix Port Name Pin Name P51/ BREQ-B P50/ BREQO-B MCU Operating Mode Reset Hardware Standby Software Standby Bus Release Mode Mode State Program Execution State Sleep Mode 1, 2, 3, 4, 7 T T 1, 2, 3, 4, 7 T T [BREQ-B input] T [BREQ-B input] BREQ-B [BREQ-B input] BREQ-B [Other than the above] Keep [Other than the above] Keep [Other than the above] I/O port [BREQO-B output] [BREQO-B output] [BREQO-B output] BREQO-B BREQO-B BREQO-B [Other than the above] K
PAGE 1391
H8S/2456, H8S/2456R, H8S/2454 Group Appendix Port Name Pin Name MCU Operating Mode Reset Hardware Standby Software Standby Bus Release Mode Mode State Program Execution State Sleep Mode PA4/A20 1, 2 T T [Address output] A20 to A16 [Address output] T [Address output] A20 to A16 [Other than the above] Keep [Other than the above] I/O port T [Address output] A15 to A8 [Address output] T [Address output] A15 to A8 [Other than the above] Keep [Other than the above] I/O port L PA3/A19 [OPE =
PAGE 1392
H8S/2456, H8S/2456R, H8S/2454 Group Appendix Port Name Pin Name MCU Operating Mode Reset Hardware Standby Software Standby Bus Release Mode Mode State Program Execution State Sleep Mode Port C 1, 2 T T [Address output] A7 to A0 [Address output] T [Address output] A7 to A0 [Other than the above] Keep [Other than the above] I/O port L [OPE = 0] T [OPE = 1] Keep 3, 4, 7 T T [Address output, OPE = 0] T [Address output, OPE = 1] Keep [Other than the above] Keep Port D Port E 1, 2, 4 T T
PAGE 1393
H8S/2456, H8S/2456R, H8S/2454 Group Appendix Port Name Pin Name MCU Operating Mode Reset Hardware Standby Software Standby Bus Release Mode Mode State Program Execution State Sleep Mode Port E 3, 7 8-bit T bus T Keep Keep I/O port 16bit bus T [Data bus, address/data multiplexed bus] T [Data bus, address/data multiplexed bus] T [Other than the above] Keep [Other than the above] Keep [Data bus, address/data multiplexed bus] D7 to D0, AD7 to AD0 [Clock output] H [Clock output] Clock output
PAGE 1394
H8S/2456, H8S/2456R, H8S/2454 Group Appendix Port Name Pin Name MCU Operating Mode Reset Hardware Standby Software Standby Bus Release Mode Mode State Program Execution State Sleep Mode PF3/LWR 1, 2, 4 H T 3, 7 T [LWR output] T [LWR output] LWR [Other than the above] Keep [Other than the above] I/O port [LCAS, DQML output, OPE = 0] T [LCAS, DQML output] T [LCAS, DQML output] LCAS, DQML [LCAS, DQML output, OPE = 1] H [Other than the above] Keep [Other than the above] I/O port [UCAS, DQM
PAGE 1395
H8S/2456, H8S/2456R, H8S/2454 Group Port Name Pin Name PG5/ BACK-A PG4/ Appendix MCU Operating Mode Reset Hardware Standby Software Standby Bus Release Mode Mode State Program Execution State Sleep Mode 1, 2, 3, 4, 7 T T 1, 2, 3, 4, 7 T T BREQO-A PG3/CS3 1, 2, 3, 4, 7 T 1 RAS3/CAS* T PG2/CS2 1 RAS2/RAS* [BACK-A output] BACK-A [BACK-A output] BACK-A [BACK-A output] BACK-A [Other than the above] Keep [Other than the above] Keep [Other than the above] I/O port [BREQO-A output] [BREQO-A out
PAGE 1396
H8S/2456, H8S/2456R, H8S/2454 Group Appendix Port Name Pin Name PH3/OE-A/ 1 CKE-A* / CS7 MCU Operating Mode Reset Hardware Standby Software Standby Bus Release Mode Mode State 1, 2, 3, 4, 7 T T [OE-A, CS, CKE-A output, OPE = 0] T [OE-A output, OPE = 1] H Program Execution State Sleep Mode [OE-A, CS, CKE-A output] T [OE-A, CKE-A output] OE-A, CKE-A [Other than the above] Keep [CS output] CS [CS output] T [CS output] CS [Other than the above] Keep [Other than the above] I/O port [CS output, O
PAGE 1397
H8S/2456, H8S/2456R, H8S/2454 Group Port Name Pin Name PH1/CS5/ RAS5 1 SDRAMφ* MCU Operating Mode Reset Appendix Hardware Standby Software Standby Bus Release Mode Mode State 1, 2, 3, 4, 7 [H8S/2456R [H8S/2456R [SDPSTP = 0 in Group] Group] H8S/2456R Clock L Group] output L [H8S/2456 Group] T [H8S/2456 Group] T [SDPSTP = 1 in H8S/2456R Group, or H8S/2456 Group, CS output, OPE = 0] T [SDPSTP = 1 in H8S/2456R Group, or H8S/2456 Group, CS output, OPE = 1] H Program Execution State Sleep Mode [SDPSTP =
PAGE 1398
Appendix H8S/2456, H8S/2456R, H8S/2454 Group DDR: Data direction register OPE: Output port enable Notes: 1. Not supported by the H8S/2456 Group. 2. Low output if a watchdog timer overflow occurs when WT/IT is 1. Page 1368 of 1408 R01UH0309EJ0500 Rev. 5.
PAGE 1399
H8S/2456, H8S/2456R, H8S/2454 Group Table A.
PAGE 1400
H8S/2456, H8S/2456R, H8S/2454 Group Appendix Port Name Pin Name P50/ BREQO-B MCU Operating Mode Reset Hardware Standby Mode 1, 2, 3, 4, 7 T T Software Standby Mode Bus Release State Program Execution State Sleep Mode [BREQO-B output] BREQO-B [BREQO-B output] BREQO-B [BREQO-B output] BREQO-B [Other than the above] Keep [Other than the above] Keep [Other than the above] I/O port Port 8 1, 2, 3, 4, 7 T T Keep Keep I/O port P95/DA3 1, 2, 3, 4, 7 T T [DAOE3 = 1] Keep Keep Input por
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H8S/2456, H8S/2456R, H8S/2454 Group Appendix Port Name Pin Name MCU Operating Mode Reset Hardware Standby Mode PA6/A22 1, 2, 3, 4, 7 T T PA5/A21 Software Standby Mode Bus Release State [Address output, [Address output] OPE = 0] T T [Other than the [Address output, above] OPE = 1] Keep Keep Program Execution State Sleep Mode [Address output] A22 to A21 [Other than the above] I/O port [Other than the above] Keep PA4/A20 1, 2 L T PA3/A19 [OPE = 0] T T [Address output] A20 to A16 [OPE = 1
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H8S/2456, H8S/2456R, H8S/2454 Group Appendix Port Name Pin Name MCU Operating Mode Reset Hardware Standby Mode Port B 1, 2 L T Software Standby Mode Bus Release State [OPE = 0] T T Program Execution State Sleep Mode [Address output] A15 to A8 [OPE = 1] Keep 4 T T [Address output, [Address output] OPE = 0] T T [Other than the [Address output, above] OPE = 1] Keep Keep [Address output] A15 to A8 [Other than the above] I/O port [Other than the above] Keep 3, 7 T T [Address output, [Addre
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H8S/2456, H8S/2456R, H8S/2454 Group Appendix Port Name Pin Name MCU Operating Mode Reset Hardware Standby Mode Port C 1, 2 L T Software Standby Mode Bus Release State [OPE = 0] T T Program Execution State Sleep Mode [Address output] A7 to A0 [OPE = 1] Keep 4 T T [Address output, [Address output] OPE = 0] T T [Other than the [Address output, above] OPE = 1] Keep Keep [Address output] A7 to A0 [Other than the above] I/O port [Other than the above] Keep 3, 7 T T [Address output, [Address
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H8S/2456, H8S/2456R, H8S/2454 Group Appendix Port Name Pin Name Port E PF7/φ PF6/AS MCU Operating Mode Reset Hardware Standby Mode Software Standby Mode Bus Release State Program Execution State Sleep Mode 1, 2, 4 8-bit bus T T Keep Keep I/O port 16-bit bus T T T T D7 to D0, AD7 to AD0 3, 7 8-bit bus T T Keep Keep I/O port 16-bit bus T [Data bus, address/data multiplexed bus] T [Data bus, address/data multiplexed bus] T [Other than the above] Keep [Other than the above] Kee
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H8S/2456, H8S/2456R, H8S/2454 Group Appendix Port Name Pin Name MCU Operating Mode Reset Hardware Standby Mode PF3/LWR 1, 2, 4 H T 3, 7 T Software Standby Mode Bus Release State Program Execution State Sleep Mode [LWR output, OPE = 0] T [LWR output] T [LWR output] LWR [Other than the above] Keep [Other than the above] I/O port [LCAS output] T [LCAS output] LCAS [CS output] T [CS output] CS [Other than the above] Keep [Other than the above] I/O port [UCAS output] T [UCAS output] UC
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H8S/2456, H8S/2456R, H8S/2454 Group Appendix Port Name Pin Name PF0/ WAIT-A/ OE-A MCU Operating Mode Reset Hardware Standby Mode 1, 2, 3, 4, 7 T T Software Standby Mode Bus Release State Program Execution State Sleep Mode [WAIT-A input] T [WAIT-A input] T [WAIT-A input] WAIT-A [OE-A output] T [OE-A output, OPE = 0] T [OE-A output, OPE = 0] OE-A [Other than the above] Keep [Other than the above] I/O port [BREQ-A input] T [BREQ-A input] BREQ-A [BREQ-A input] BREQ-A [Other than the above
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H8S/2456, H8S/2456R, H8S/2454 Group Port Name Pin Name PG3/CS3/ RAS3 Appendix MCU Operating Mode Reset Hardware Standby Mode 1, 2, 3, 4, 7 T T PG2/CS2/ RAS2 Software Standby Mode Bus Release State Program Execution State Sleep Mode [CS output, OPE = 0] T [CS output] T [CS output] CS [Other than the above] Keep [Other than the above] I/O port [CS output] T [CS output] CS [Other than the above] Keep [Other than the above] I/O port [CS output, OPE = 1] H PG1/CS1 [Other than the above] K
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H8S/2456, H8S/2456R, H8S/2454 Group Appendix B. Package Dimensions JEITA Package Code P-LQFP144-20x20-0.50 RENESAS Code PLQP0144KA-A Previous Code 144P6Q-A / FP-144L / FP-144LV MASS[Typ.] 1.2g HD *1 D 108 73 109 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
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H8S/2456, H8S/2456R, H8S/2454 Group JEITA Package Code P-TFLGA145-9x9-0.65 Appendix RENESAS Code PTLG0145JB-A Previous Code - MASS[Typ.] 0.15g D w S B E w S A x4 v y1 S A S y S e A ZD e N M L K J B H G F E D ZE C B Reference Symbol Dimension in Millimeters Min 9.0 E 9.0 1 2 3 4 5 6 7 φb 8 9 10 11 12 13 0.15 w 0.20 A 1.2 A1 b 0.65 0.30 0.35 0.40 0.08 x φxn S A B Max v e A Nom D y 0.1 y1 0.20 SD SE ZD 0.6 ZE 0.6 Figure B.
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H8S/2456, H8S/2456R, H8S/2454 Group Appendix JEITA Package Code P-LQFP120-14x14-0.40 RENESAS Code PLQP0120LA-A Previous Code 120P6R-A / FP-120B / FP-120BV MASS[Typ.] 0.7g HD *1 D 90 61 60 91 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
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H8S/2456, H8S/2456R, H8S/2454 Group JEITA Package Code P-LQFP120-16x16-0.50 Appendix RENESAS Code PLQP0120KA-A Previous Code — MASS[Typ.] 0.9g HD *1 D 90 61 60 91 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
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H8S/2456, H8S/2456R, H8S/2454 Group Appendix C. Treatment of Unused Pins The treatments of unused pins are listed in table C.1 Table C.
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H8S/2456, H8S/2456R, H8S/2454 Group Appendix Pin Name Mode 1 PF7 • This pin is left open in the initial state for the φ output. PF6 • This pin is left open in the initial state for the AS output. PF5 • This pin is left open in the initial state for the RD output. PF4 • This pin is left open in the initial state for the HWR output. PF3 • This pin is left open in the initial state for the LWR output. PG0 • This pin is left open in the initial state for the CS0 output.
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Appendix Page 1384 of 1408 H8S/2456, H8S/2456R, H8S/2454 Group R01UH0309EJ0500 Rev. 5.
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Main Revisions and Additions in this Edition Item Page Revision (See Manual for Details) 4.3 Reset 100 Amended A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 15 ms at power-up. To reset this LSI during operation, hold the RES pin low for at least 2 ms. 7.
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Item Page Revision (See Manual for Details) Table 7.4 DMAC Transfer Modes 354, 355 Amended Transfer Source • TPU channel 0 to 5 compare match/input capture A interrupt • SCI transmit data empty interrupt • SCI receive data full interrupt • A/D converter conversion end interrupt • External request • TPU channel 0 to 5 compare match/input capture A interrupt • SCI transmit data empty interrupt • SCI receive data full interrupt • A/D converter conversion end interrupt • External request 7.5.
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Item Page Revision (See Manual for Details) 10.1.5 Pin Functions 527 (1) Pin Functions of H8S/2456 Group and H8S/2456R Group • P17/PO15/TIOCB2/ TCLKD/EDRAK3/ SCS0-A Notes amended 3. When using as SCS0-A input, set SCS0S1 and SCS0S0 in PFCR5 to B'00 before other register setting. 4. When using as SCS0-A output, set SCS0S1 and SCS0S0 in PFCR5 to B'00 before other register setting. 5. When using as SCS0-A input/output, set SCS0S1 and SCS0S0 in PFCR5 to B'00 before other register setting.
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Item • • • Page Revision (See Manual for Details) P15/DACK1/PO13/ 541 TIOCB1/TCLKC/ SSI0-A P14/DACK0/PO12/ 543 TIOCA1/SSO0-A P10/DREQ0/PO8/ TIOCA0 10.2.5 Pin Functions 548 555 • P25/PO5-A/ TIOCB4-A/ IRQ13-B/WAIT-B/ VBUS • Modes 3 and 7 (EXPE = 0) • 557 P20/PO0-A/ TIOCA3-A/IRQ8-B/ PUPD+ • • P25/WAIT-B/ PO5-A/TIOCB4-A/ TMO1-A/VBUS Modes 3 and 7 (EXPE = 0) Page 1388 of 1408 3. When using as SSI0-A input, set SSI0S1 and SSI0S0 in PFCR5 to B'00 before other register setting. 4.
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Item Page Revision (See Manual for Details) • 562 P20/PO0-A/ TIOCA3-A/ TMRI0-A/PUPD+ 10.3.5 Pin Functions • • • • • • 576 P52/SCK2/IRQ2-A/ BACK-B/PO4-B/ TIOCA4-B/TMO0-B Modes 3 and 7 (EXPE = 0) P51/RxD2/IRQ1-A/ 579 SCL3/BREQ-B/ PO2-B/TIOCC3-B/ TMCI0-B Modes 3 and 7 (EXPE = 0) P50/TxD2/IRQ0-A/ 581 SDA3/BREQO-B/ PO0-B/TIOCA3-B/ TMRI0-B Modes 3 and 7 (EXPE = 0) 10.6.5 Pin Functions • P65/IRQ13-A/ DACK1/TMO1-A • P64/IRQ12-A/ DACK0/TMO0-A R01UH0309EJ0500 Rev. 5.00 Sep 24, 2012 4.
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Item Page Revision (See Manual for Details) • P63/IRQ11-A/ TEND1/TMCI1-A 585 P62/IRQ10-A/ TEND0/TMCI0-A 586 P61/IRQ9A/DREQ1/ TMRI1-A 586 • • • P60/IRQ8A/DREQ0/ TMRI0-A 10.7.5 Pin Functions 3. 587 591 P85/EDACK3/ IRQ5-B/SCK3/ PO5-B/TIOCB4-B/ TMO1-B • Modes 3 and 7 (EXPE = 0) • P83/ETEND3/ IRQ3-B/RxD3/ PO3-B/TIOCD3-B/ TMCI1-B • Modes 3 and 7 (EXPE = 0) Page 1390 of 1408 594 When using as TMCI1-A input, set TMRS in PFCR3 to 0 before other register setting. Notes amended 3.
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Item Page Revision (See Manual for Details) • 595 P81/EDREQ3/ IRQ1-B/TxD3/ PO1-B/TIOCB3-B/ TMRI1-B (2) Pin Functions of H8S/2454 Group • • • 597 P85/SCK3/PO5-B/ TIOCB4-B/TMO1-B P83/PO3-B/ TIOCD3-B/ TMCI1-B/RxD3 P81/PO1-B/ TIOCB3-B/ TMRI1-B/TxD3 10.9.6 Pin Functions 598 599 609 Notes amended 4. When using as PO1-B output, set PPGS in PFCR3 to 1 before other register setting. 5. When using as TIOCB3-B input/output, set TPUS in PFCR3 to 1 before other register setting. 6.
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Item Page Revision (See Manual for Details) • PA6/A22/IRQ6-A/ SSI0-B 610 • Modes 3 and 7 • PA5/A21/IRQ5-A/ SSCK0-B • Modes 3 and 7 • • PA4/A20/IRQ4-A/ SCS0-B PA3/A19/SCK4-B 612 613 615 Notes amended 2. When using as SSI0-B input, set SSI0S1 and SSI0S0 in PFCR5 to B'01 before other register setting. 3. When using as SSI0-B output, set SSI0S1 and SSI0S0 in PFCR5 to B'01 before other register setting. Notes amended 2.
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Item • Page Revision (See Manual for Details) 6 PF2/LCAS/DQML* / 659 Notes amended IRQ15-A/SSI0-C 2. (H8S/2456 Group and H8S/2456R Group) When using as SSI0-C input, set SSI0S1 and SSI0S0 in PFCR5 to B'10 before other register setting. 3. When using as SSI0-C output, set SSI0S1 and SSI0S0 in PFCR5 to B'10 before other register setting. • Modes 3 and 7 (EXPE = 0) • PF2/CS6/LCAS/SSI 661 0-C (H8S/2454 Group) Notes amended 1.
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Item Page Revision (See Manual for Details) • 667 • PF0/WAIT-A/ ADTRG0-B/ SCS0-C/OE-A (H8S/2454 Group) Modes 3 and 7 (EXPE = 0) 15.3.7 Serial Status Register (SSR) 881 Smart Card Interface Mode (When SMIF bit in SCMR is 1) Notes amended 3. When using as SCS0-C input, set SCS0S1 and SCS0S0 in PFCR5 to B'10 before other register setting. 4. When using as SCS0-C output, set SCS0S1 and SCS0S0 in PFCR5 to B'10 before other register setting. 5.
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Item Page Revision (See Manual for Details) 17.7 Usage Notes 1056, Added 1057 5. Restriction on Setting Transfer Rate in Use of Multi-Master 6. Restriction on Use of Bit Manipulation Instructions to Set MST and TRS in Use of Multi-Master 7. Note on Master Receive Mode 8. Notes on Changing from Master Transmit Mode to Master Receive Mode 18.3.
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Item Page Revision (See Manual for Details) 20.3.5 SS Status Register (SSSR) 1112, Deleted 1113 Bit Bit Name 6 ORER Description [Clearing condition] When writing 0 after reading ORER = 1 (When the CPU is used to clear this flag by writing 0 hile the corresponding interrupt is enabled, be sure to ead the flag after writing 0 to it.
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Item Page Revision (See Manual for Details) Figure 22.2 Setting and 1154 Clearing EW0 Mode Amended Programming control program*4 Write 0 to the FMCMDEN bit and then write 1 to it (user program mode enabled).*1 Clear CBIDB to 0. Write 1 to the CBIDB bit (user program mode disabled). Jump to a desired address in the flash memory. Notes: 1. 2. 3. Table 26.2 DC Characteristics (1) To set the FMCMDEN bit to 1, write 0 to the bit and then write 1 to it in a row.
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Item Page Revision (See Manual for Details) Table 26.15 Flash Memory Characteristics 1304 Table 26.29 Flash Memory Characteristics 1321 Deleted and amended Item Symbol Test Conditions Standard Value Applicable Area Max. Programming ROM ⎯ Data flash area ⎯ Programming time Programming ROM 4000 (per 4 bytes) Data flash area 4000 Erase time (per 1 block) Programming ROM 3000 Data flash area 3000 Programming ROM 3.
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Item Page Revision (See Manual for Details) Table 26.
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Page 1400 of 1408 R01UH0309EJ0500 Rev. 5.
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Index Numerics 16-Bit counter mode ............................... 839 16-Bit timer pulse unit (TPU)................. 693 8-Bit timer (TMR) .................................. 821 A A/D conversion accuracy...................... 1086 A/D Converter ...................................... 1059 A/D converter activation......................... 776 Absolute accuracy................................. 1086 Absolute address....................................... 75 Acknowledge ..............................
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Data transfer controller (DTC) ............... 477 Data transfer instructions.......................... 64 DMA controller (DMAC)....................... 321 DMTEND0A .......................................... 133 DMTEND0B .......................................... 133 DMTEND1A .......................................... 133 DMTEND1B .......................................... 133 DRAM interface ............................. 209, 223 DTC vector table .................................... 487 Dual address mode...
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N Q NMI ........................................................ 148 NMI interrupt.......................................... 129 Nonlinearity error ................................. 1086 Non-overlapping pulse output ................ 813 Normal mode ...................... 49, 50, 368, 494 Normal transfer mode ............................. 431 Quantization error ................................. 1086 O Offset error ........................................... 1086 On-board programming .....................
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DMAWER.......................................... 348 DRACCR............................................ 181 DRAMCR........................................... 173 DTCER............................................... 483 DTVECR ............................................ 483 EDACR .............................................. 419 EDDAR .............................................. 411 EDMDR.............................................. 414 EDSAR............................................... 411 EDTCR.....
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PGDR ................................................. 670 PHDDR............................................... 675 PHDR ................................................. 677 PLLCR.............................................. 1204 PMR.................................................... 807 PODR ................................................. 802 PORT1................................................ 524 PORT2................................................ 550 PORT3........................................
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Sequential mode ..................................... 356 Serial communication interface .............. 859 Serial Communication Interface Specification ......................................... 1171 Setup stage.............................................. 999 Shift instructions....................................... 67 Single address mode ....................... 365, 425 Single mode .......................................... 1076 Slave address ........................................ 1038 Slave-address...
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V W Valid strobes ........................................... 196 Vector number for the software activation interrupt .................................................. 483 Wait control .................................... 205, 219 Watchdog timer (WDT) .......................... 847 Waveform output by compare match...... 745 WOVI...................................................... 854 Write data buffer ..................................... 310 Write data buffer function.......................
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Page 1408 of 1408 R01UH0309EJ0500 Rev. 5.
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H8S/2456, H8S/2456R, H8S/2454 Group User’s Manual: Hardware Publication Date: Rev.1.00 Rev.5.
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http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada Tel: +1-905-898-5441, Fax: +1-905-898-3220 Renesas Electronics Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.
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H8S/2456, H8S/2456R, H8S/2454 Group R01UH0309EJ0500 (REJ09B0467-0350)