Datasheet

Section 10 I/O Ports
Page 526 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
10.1.5 Pin Functions
Port 1 pins also function as the pins for PPG outputs, TPU I/Os, EXDMAC I/Os (H8S/2456 group,
H8S/2456R group), SSU I/Os, and DMAC I/Os (H8S/2454 group). The correspondence between
the register specification and the pin functions is shown below.
(1) Pin Functions of H8S/2456 Group and H8S/2456R Group
• P17/PO15/TIOCB2/TCLKD/EDRAK3/SCS0-A
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, TPU channel 2 settings (by bits MD3 to MD0 in TMDR_2, bits IOB3 to
IOB0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2), bits TPSC2 to TPSC0 in TCR_0
and TCR_5, bit NDER15 in NDERH of PPG, bit EDRAKE in EDMDR_3 of EXDMAC, bits
MSS, CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of SSU, bits SCS0S1 and
SCS0S0 in PFCR5, and bit P17DDR.
• Modes 1, 2, and 4 Modes 3 and 7 (EXPE = 1)
SSU settings (1) in table below (2) in
table
below
(4) in
table
below
(3) in
table
below
EDRAKE 0 1 ⎯
TPU channel
2 settings
(1) in table
below
(2) in table below ⎯ ⎯
P17DDR ⎯ 0 1 1 ⎯ 0
*
6
0
*
6
⎯
NDER15 ⎯ ⎯ 0 1 ⎯ ⎯
P17
input
P17
output
PO15
output
EDRAK3
output
TIOCB2
output
TIOCB2 input
*
1
Pin function
TCLKD input
*
2
SCS0-A
input
*
3
*
7
SCS0-A
I/O
*
5
*
7
SCS0-A
output
*
4
*
7