Datasheet

Section 6 Bus Controller (BSC)
R01UH0309EJ0500 Rev. 5.00 Page 227 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
6.7.5 Basic Timing
Figure 6.33 shows the basic access timing for DRAM space.
The four states of the basic timing consist of one T
p
(precharge cycle) state, one T
r
(row address
output cycle) state, and the T
c1
and two T
c2
(column address output cycle) states.
T
p
RASn (CSn)
Read
Write
UCAS, LCAS
WE (HWR)
OE (RD)
Data bus
WE (HWR)
OE (RD)
Data bus
Address bus
φ
T
r
T
c1
T
c2
Row address
High
High
Column address
Note: n = 2 to 5
Figure 6.33 DRAM Basic Access Timing (RAST = 0, CAST = 0)