Datasheet

Section 20 Synchronous Serial Communication Unit (SSU)
Page 1134 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
20.4.7 Clock Synchronous Communication Mode
In clock synchronous communication mode, data communications are performed via three lines:
clock line (SSCK), data input line (SSI), and data output line (SSO).
(1) Initial Settings in Clock Synchronous Communication Mode
Figure 20.12 shows an example of the initial settings in clock synchronous communication mode.
Before data transfer, clear both the TE and RE bits in SSER to 0 to set the initial values.
Note: Before changing operating modes and communications formats, clear both the TE and RE
bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0
does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the
previous values.
Start setting initial values
[1]
[2]
[3]
[4]
End
Clear a bit in DDR to 0
Set SSUMS in SSCRL to 1 and
specify bits DATS1 and DATS0
Specify MSS and SCKS in SSCRH
Specify CPOS, CKS2, CKS1, and
CKS0 bits in SSMR
Specify TE, RE, TEIE, TIE, RIE, and
CEIE bits in SSER simultaneously
Specify SDOS, SSCKOS, SCSOS,
TENDSTS, SCSATS, and
SSODTS bits in SSCR2
Clear TE and RE bits in SSER to 0
[1] When the pin is used as an input.
[2] Specify master/slave mode selection and SSCK pin
selection.
[3] Selects clock synchronous communication mode and
specify transmit/receive data length.
[4] Specify clock polarity selection and transfer clock rate
selection.
[5] Enables/disables interrupt request to the CPU.
[5]
Figure 20.12 Example of Initial Settings in Clock Synchronous Communication Mode