Datasheet

Section 15 Serial Communication Interface (SCI, IrDA)
Page 934 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(DE)
Ds D0 D1 D2 D3 D4Ds
Transfer
frame n+1
Retransferred frame
nth transfer frame
TDRE
TEND
[1]
FER/ERS
Transfer to TSR from TDR Transfer to TSR from TDR
Transfer to TSR
from TDR
[2] [4]
[3]
Figure 15.26 Retransfer Operation in SCI Transmit Mode
The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag
generation timing is shown in figure 15.27.
Ds D0 D1 D2 D3 D4 D5 D6 D7 DpI/O data
12.5 etu
TXI
(TEND interrupt)
11.0 etu
DE
Guard
time
When GM = 0
When GM = 1
: Start bit
: Data bits
: Parity bit
: Error signal
Legend:
Ds
D0 to D7
Dp
DE
Note: etu (Elementary Time Unit): Time for transfer of 1 bit
Figure 15.27 TEND Flag Generation Timing in Transmission Operation