Datasheet

Section 13 8-Bit Timers (TMR)
R01UH0310EJ0500 Rev. 5.00 Page 849 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
13.8.4 Contention between Compare Matches A and B
If compare match events A and B occur at the same time, the 8-bit timer operates in accordance
with the priorities for the output statuses set for compare match A and compare match B, as shown
in table 13.5.
Table 13.5 Timer Output Priorities
Output Setting Priority
Toggle output High
1 output
0 output
No change Low
13.8.5 Switching of Internal Clocks and TCNT Operation
TCNT may increment erroneously when the internal clock is switched over. Table 13.6 shows the
relationship between the timing at which the internal clock is switched (by writing to the CKS1,
CKS0, ICKS1, and ICKS0 bits) and the TCNT operation.
When the TCNT clock is generated from an internal clock, the rising edge or falling edge of the
internal clock pulse is detected. Therefore, when the falling edge is selected, if clock switching
causes a change from high to low level, as shown in case 3 in table 13.6, a TCNT clock pulse is
generated and the TCNT incremented on the assumption that the switchover is a falling edge. This
is the same as when the rising edge is selected.
The erroneous incrementation can also happen when switching between the rising edge and falling
edge of an internal clock or switching between internal and external clocks.