Datasheet

Section 13 8-Bit Timers (TMR)
Page 848 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
13.8.3 Contention between TCOR Write and Compare Match
During the T
2
state of a TCOR write cycle, the TCOR write has priority and the compare match
signal is inhibited even if a compare match event occurs as shown in figure 13.13.
Address
φ
TCOR address
Internal write signal
TCNT
TCOR N M
T
1
T
2
TCOR write cycle by CPU
TCOR write data
N N + 1
Compare match signal
Inhibited
Figure 13.13 Contention between TCOR Write and Compare Match