Datasheet

Section 13 8-Bit Timers (TMR)
R01UH0310EJ0500 Rev. 5.00 Page 847 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
13.8.2 Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T
2
state of a TCNT write cycle, the write
takes priority and the counter is not incremented. Figure 13.12 shows this operation.
Address
φ
TCNT address
Internal write signal
TCNT input clock
TCNT N M
T
1
T
2
TCNT write cycle by CPU
Counter write data
Figure 13.12 Contention between TCNT Write and Increment