Datasheet

Section 13 8-Bit Timers (TMR)
Page 842 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
13.5.3 Timing of Timer Output when Compare-Match Occurs
When compare match A or B occurs, the timer output changes as specified by bits OS3 to OS0 in
TCSR. Figure 13.7 shows the timing when the output is set to toggle at compare match A.
Compare match A
signal
φ
Timer output pin
Figure 13.7 Timing of Timer Output
13.5.4 Timing of Compare Match Clear
TCNT is cleared when compare match A or B occurs, depending on the settings of the CCLR1
and CCLR0 bits in TCR and the TMRIS bit in TCCR. Figure 13.8 shows the timing of this
operation.
N H'00
Compare match
signal
φ
TCNT
Figure 13.8 Timing of Compare Match Clear