Datasheet

Section 13 8-Bit Timers (TMR)
R01UH0310EJ0500 Rev. 5.00 Page 839 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
13.4.2 Reset Input
Figure 13.3 shows an example in which the 8-bit timer is used to generate a pulse output with a
selected delay in response to the TMRI input. The control bits are set as follows:
[1] The CCLR0 bit in TCR is set to 1 and the TMRIS bit in TCCR is set to 1 so that TCNT is
cleared at the high level of the TMRI input.
[2] In TCSR, bits OS3 to OS0 are set to B'0110, causing the output to change to 1 at a TCORA
compare match and to 0 at a TCORB compare match.
With these settings, the 8-bit timer provides output of pulses whose delay from the TMRI input is
determined by TCORA and the pulse width determined by (TCORB TCORA).
TCORB
TCORA
H'00
TMRI
TMO
TCNT
Figure 13.3 Example of Reset Input