Datasheet

Section 13 8-Bit Timers (TMR)
Page 836 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
• TCSR_1
Bit Bit Name Initial Value R/W Description
7 CMFB 0 R/(W)
*
Compare Match Flag B
[Setting condition]
• Set when TCNT matches TCORB
[Clearing conditions]
• Cleared by reading CMFB when CMFB = 1,
then writing 0 to CMFB
• When DTC is activated by CMIB interrupt while
DISEL bit of MRB in DTC is 0
6 CMFA 0 R/(W)
*
Compare Match Flag A
[Setting condition]
• Set when TCNT matches TCORA
[Clearing conditions]
• Cleared by reading CMFA when CMFA = 1,
then writing 0 to CMFA
• When DTC is activated by CMIA interrupt while
DISEL bit of MRB in DTC is 0
5 OVF 0 R/(W)
*
Timer Overflow Flag
[Setting condition]
• Set when TCNT overflows from H'FF to H'00
[Clearing condition]
• Cleared by reading OVF when OVF = 1, then
writing 0 to OVF
4 ⎯ 1 R Reserved
This bit is always read as 1 and cannot be
modified.