Datasheet

Section 13 8-Bit Timers (TMR)
Page 828 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Figure 13.1 shows a block diagram of the 8-bit timer module (TMR_0 and TMR_1).
φ/2
φ/8
φ/32
φ/64
φ/1024
φ/8192
Counter clock 1
Counter clock 0
Compare match A1
Compare match A0
Counter clear 1
CMIA0
CMIB0
OVI0
CMIA1
CMIB1
OVI1
Interrupt signals
TMO0
TMRI0
TCORA_0
Comparator A_0
Comparator B_0
TCORB_0
TCSR_0
TCR_0
TCORA_1
Comparator A_1
TCNT_1
Comparator B_1
TCORB_1
TCSR_1
TCR_1
TMCI0
TMCI1
TCNT_0
Overflow 1
Overflow 0
Compare match B1
Compare match B0
TMO1
TMRI1
Counter clear 0
Channel 1
(TMR_1)
TCCR_0 TCCR_1
Channel 0
(TMR_0)
Internal clock sources
Clock select
TCORA_0:
TCNT_0:
TCORB_0:
TCSR_0:
TCR_0:
TCCR_0:
Time constant register A_0
Timer counter_0
Time constant register B_0
Timer control/status register_0
Timer control register_0
Timer counter control register_0
TCORA_1:
TCNT_1:
TCORB_1:
TCSR_1:
TCR_1:
TCCR_1:
Time constant register A_1
Timer counter_1
Time constant register B_1
Timer control/status register_1
Timer control register_1
Timer counter control register_1
Internal bus
A/D
conversion
start request
signal
Control logic
[Legend]
Figure 13.1 Block Diagram of 8-Bit Timer Module