Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
R01UH0310EJ0500 Rev. 5.00 Page 793 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
11.10 Usage Notes
11.10.1 Module Stop Function Setting
TPU operation can be disabled or enabled using the module stop control register. The initial
setting is for TPU operation to be halted. Register access is enabled by clearing the module stop
state. For details, refer to section 23, Power-Down Modes.
11.10.2 Input Clock Restrictions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a
narrower pulse width.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 11.45 shows the input clock
conditions in phase counting mode.
Overlap
Phase
diffe-
rence
Phase
diffe-
rence
Overlap
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Pulse width Pulse width
Pulse width Pulse width
Notes: Phase difference and overlap
Pulse width
: 1.5 states or more
: 2.5 states or more
Figure 11.45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode