Datasheet

Section 10 I/O Ports
R01UH0310EJ0500 Rev. 5.00 Page 675 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
10.15.1 Port G Data Direction Register (PGDDR)
The individual bits of PGDDR specify input or output for the pins of port G. PGDDR cannot be
read; if it is, an undefined value will be read.
Bit Bit Name Initial Value R/W Description
7 ⎯ 0 ⎯ Reserved
6 PG6DDR 0 W
5 PG5DDR 0 W
4 PG4DDR 0 W
3 PG3DDR 0 W
2 PG2DDR 0 W
1 PG1DDR 0 W
0 PG0DDR 1/0* W
• Modes 1, 2, and 4 Modes 3 and 7 (EXPE = 1)
Pins PG6 and PG5 function as bus control
input/output pins (BREQ and BACK) when the
appropriate bus controller settings are made.
Otherwise, these pins are I/O ports, and their
functions can be switched with PGDDR.
The PG4 pin function as a bus control input/output
pin (BREQO) when the appropriate bus controller
settings are made. Otherwise, operations differ
between the H8S/2426 and H8S/2426R Groups
and H8S/2424 Group.
[H8S/2426 Group and H8S/2426R Group]
The PG4 pin is a general I/O port and the function
can be switched with PG4DDR.
[H8S/2424 Group]
When the CS output enable bit (CS4E) is 1, the
PG4 pin functions as a CS4 output pin when the
PG4DDR is set to 1, and as an input port when the
bit is cleared to 0. When the CS output enable bit
(CS4E) is 0, the PG4 pin is a general I/O port, and
the function can be switched with PG4DDR.
When the CS output enable bits (CS3E to CS0E)
are set to 1, pins PG3 to PG0 function as CS
output pins when the corresponding PGDDR bit is
set to 1, and as input ports when the bit is cleared
to 0. When the CS output enable bits (CS3E to
CS0E) are cleared to 0, pins PG3 to PG0 are I/O
ports, and their functions can be switched with
PGDDR.
• Modes 3 and 7 (EXPE = 0)
Pins PG6 to PG0 are I/O ports, and their functions
can be switched with PGDDR.
Note: * PG0DDR is initialized to 1 in modes 1 and 2, and to 0 in modes 3, 4, and 7.