Datasheet

Section 10 I/O Ports
R01UH0310EJ0500 Rev. 5.00 Page 643 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
• PC2/A2/TIOCC9
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, TPU channel 9 settings (by bits MD3 to MD0 in TMDR_9, bits IOC3 to
IOC0 in TIORL_9, and bits CCLR2 to CCLR0 in TCR_9), and bit PC2DDR.
Operating
mode
1, 2 4 3, 7 (EXPE = 1) 3, 7 (EXPE = 0)
TPU channel
9 settings
⎯ ⎯ (1) in table
below
(2) in table below
PC2DDR ⎯ 0 1 ⎯ 0 1
PC2 input PC2 output Pin function A2 output PC2 input A2 output TIOCC9
output
TIOCC9 input*
1
TPU channel 9
settings
(2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000 B'001x B'0010 B'0011
IOC3 to IOC0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00 Other than B'xx00
CCLR2 to
CCLR0
⎯ ⎯ ⎯ ⎯ Other than
B'101
B'101
Output function ⎯ Output
compare
output
⎯ PWM*
2
mode
1 output
PWM mode
2 output
⎯
[Legend]
x: Don't care
Notes: 1. TIOCC9 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx.
2. TIOCD9 output disabled. Output disabled and settings (2) effective when BFA = 1 or
BFB = 1 in TMDR_9.