Datasheet

Section 10 I/O Ports
Page 584 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
• P50/TxD2/IRQ0-A/SDA3/BREQO-B/PO0-B/TIOCA3-B/TMRI0-B
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit BRLE of the bus controller, bit BREQOE, bit ICE in ICCRA_3 of the
I2C, bits MD3 to MD0 in TMDR_3 of TPU, bits IOA3 to IOA0 in TIORH_3, TPU channel 3
settings by bits CCLR2 to CCLR0 in TCR_3, bit NDER0 in NDERL of PPG, bit TE in SCR_2
of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, bit BREQOS in PFCR4, bit P50DDR,
and bit ITS0 in ITSR of the interrupt controller.
• Modes 1, 2, and 4 Modes 3 and 7 (EXPE = 1)
BRLE
BREQOE
BREQOS
BRLE = 0, or BRLE = 1 and BREQOE = 0,
or BRLE = 1, BREQOE = 1 and BREQOS = 0
BRLE = 1,
BREQOE = 1
and
BREQOS = 1
ICE 0 1 ⎯
TPU channel 3
settings
(1) in table
below
(2) in table below ⎯ ⎯
TE ⎯ 0 1 ⎯ ⎯
P50DDR ⎯ 0 1 1 ⎯ ⎯ ⎯
NDER0 ⎯ ⎯ 0 1 ⎯ ⎯ ⎯
P50 input P50 output
PO0-B
output*
6
TxD2 output SDA3*
5
I/O
BREQO-B
output
TIOCA3-B
output*
7
TIOCA3-B input*
1
*
7
IRQ0-A interrupt input*
2
Pin function
TMRI0-B input*
3
*
8