Datasheet

Section 10 I/O Ports
Page 578 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
10.5.3 Port 5 Register (PORT5)
PORT5 shows the pin states of port 5. PORT5 cannot be modified.
Bit Bit Name Initial Value R/W Description
7 to 4 ⎯ Undefined R Reserved
If these bits are read, they will return an undefined
value.
3 P53 ⎯* R
2 P52 ⎯* R
1 P51 ⎯* R
0 P50 ⎯* R
If the P53 to P50 bits are read while a P5DDR bit is
set to 1, the corresponding P5DR value is read. If
this register is read while a P5DDR bit is cleared to
0, the corresponding pin state is read.
Note: * Determined by the states of pins P53 to P50.
10.5.4 Port 5 Open Drain Control Register (P5ODR)
P5ODR specifies the output type of each port 5 pin.
Bit Bit Name Initial Value R/W Description
7 to 4 ⎯ All 0 ⎯ Reserved
These bits are always read as 0. Only the initial
values should be written to these bits.
3 P53ODR 0 R/W Setting this bit to 1 makes the corresponding pin an
NMOS open-drain output pin, while clearing the bit
to 0 makes the corresponding pin a CMOS output
pin.
2 P52ODR 0 R/W When BACK-B output is not selected, setting this bit
to 1 makes the corresponding pin an NMOS open-
drain output pin, while clearing the bit to 0 makes
the corresponding pin a CMOS output pin.
1 P51ODR 0 R/W Setting this bit to 1 makes the corresponding pin an
NMOS open-drain output pin, while clearing the bit
to 0 makes the corresponding pin a CMOS output
pin.
0 P50ODR 0 R/W When BREQO-B output is not selected, setting this
bit to 1 makes the corresponding pin an NMOS
open-drain output pin, while clearing the bit to 0
makes the corresponding pin a CMOS output pin.