Datasheet

Section 10 I/O Ports
Page 562 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
TPU channel 4
settings
(2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000, B'01xx B'0010 B'0011
IOB3 to IOB0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00 Other than B'xx00
CCLR1,
CCLR0
Other than
B'10
B'10
Output function Output
compare
output
PWM mode
2 output
[Legend]
x: Don't care
P24/PO4-A/TIOCA4-A/TMO0-A/RxD4-A
The pin function is switched as shown below according to the combination of the TPU channel
4 settings (by bits MD3 to MD0 in TMDR_4 of the TPU, bits IOA3 to IOA0 in TIOR_4, and
bits CCLR1 and CCLR0 in TCR_4), bits OS3 to OS0 in TCSR_0 of the 8-bit timer, bit
NDER4 in NDERL of the PPG, bit RE in SCR_4 of the SCI, bits PPGS, TPUS, TMRS in
PFCR3, bit RXD4S in PFCR4 and bit P24DDR.
RE 0 1
TPU channel 4
settings
(1) in table
below
(2) in table below
OS3 to OS0 All 0 Any bit is 1
P24DDR 0 1 1
NDER4 0 1
P24 input P24 output PO4-A
output*
3
TMO0-A
output*
5
RxD4-A
output*
6
Pin function TIOCA4-A
output*
4
TIOCA3-A input*
1
*
4