Datasheet

Section 10 I/O Ports
Page 552 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
TPU channel 5
settings
(2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011
IOA3 to IOA0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00 Other than
B'xx00
Other than B'xx00
CCLR1,
CCLR0
⎯ ⎯ ⎯ ⎯ Other than
B'01
B'01
Output function ⎯ Output
compare
output
⎯ PWM*
3
mode 1
output
PWM
mode 2
output
⎯
[Legend]
x: Don't care
Notes: 1. TIOCA5 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 = 1.
2. IRQ14-B input when the ITS14 bit in ITSR is 1.
3. TIOCB5 output disabled.
4. ADTRG1 input when EXTRGS = 0 and TRGS1 = TRGS0 = 1.
5. NMOS open-drain output regardless of P26ODR.
• P25/PO5-A/TIOCB4-A/IRQ13-B/WAIT-B
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit WAITE in BCR of the bus controller, TPU channel 4 settings by bits
MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1 and CCLR0 in
TCR_4, bit NDER5 in NDERL of PPG, bits PPGS and TPUS in PFCR3, bit WAITS in
PFCR4, bit P25DDR, and bit ITS13 in ITSR of the interrupt controller.
• Modes 1, 2, and 4 Modes 3 and 7 (EXPE = 1)
WAITE 0 1
TPU channel 4
settings
(1) in table
below
(2) in table below ⎯
P25DDR ⎯ 0 1 1 ⎯
NDER5 ⎯ ⎯ 0 1 ⎯
P25 input P25 output PO5-A output*
3
WAIT-B input*
5
TIOCB4-A
output*
4
TIOCB4-A input*
1
*
4
Pin function
IRQ13-B interrupt input*
2