Datasheet

Section 9 Data Transfer Controller (DTC)
Page 504 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
First data
transfer register
information
Second data
transfer register
information
Chain transfer
(counter = 0)
Upper 8 bits
of DAR
Input buffer
Input circuit
Figure 9.13 Chain Transfer when Counter = 0