Datasheet

Section 9 Data Transfer Controller (DTC)
Page 494 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
9.5.3 Block Transfer Mode
In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is designated as a block area. Table 9.6 lists the register function in block
transfer mode. The block size is 1 to 256. When the transfer of one block ends, the initial state of
the block size counter and the address register specified as the block area is restored. The other
address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be
specified. Once the specified number of transfers has ended, a CPU interrupt is requested.
Table 9.6 Register Function in Block Transfer Mode
Name Abbreviation Function
DTC source address register SAR Designates source address
DTC destination address register DAR Designates destination address
DTC transfer count register AH CRAH Holds block size
DTC transfer count register AL CRAL Designates block size count
DTC transfer count register B CRB Designates transfer count
First block
Transfer
Block area
Nth block
DAR
or
SAR
SAR
or
DAR
Figure 9.8 Memory Mapping in Block Transfer Mode