Datasheet

Section 8 EXDMA Controller (EXDMAC)
R01UH0310EJ0500 Rev. 5.00 Page 465 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
φ pin EDREQ EDRAK Bus cycle CPU operation ETEND
1-block-size transfer period
1 bus cycle
CPU
cycle
CPU
cycle
CPU
cycle
CPU
cycle
CPU
cycle
CPU
cycle
CPU
cycle
CPU
cycle
External
space
External
space
External
space
External
space
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
1 bus cycle
1 bus cycle
Last transfer
in block
External
space
External
space
External
space
External
space
Repeated
Figure 8.42 External Request/Cycle Steal Mode/Block Transfer Mode
(CPU Cycles/Dual Address Mode/Low Level Sensing/BGUP = 1)