Datasheet

Section 8 EXDMA Controller (EXDMAC)
Page 462 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
φ pin EDREQ EDRAK ETEND Bus cycle EDA bit
Bus release Bus release
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
01
Last transfer
in block
1-block-size transfer period
Last block
Last transfer cycle
3 cycles
Repeated
Bus release
Repeated
Figure 8.39 External Request/Cycle Steal Mode/Block Transfer Mode
(No Contention/Dual Address Mode/Low Level Sensing/BGUP = 0)