Datasheet

Section 8 EXDMA Controller (EXDMAC)
R01UH0310EJ0500 Rev. 5.00 Page 451 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Figure 8.25 shows an example of transfer when ETEND output is enabled, and word-size, single
address mode transfer (write) is performed from an external device to external 8-bit, 2-state access
space.
EXDMA write
HWR
ETEND
Address bus
φ
Bus release Bus release Bus
release
Last transfer cycle
EDACK
Bus release
EXDMA writeEXDMA write
LWR
Figure 8.25 Example of Single Address Mode (Word Write) Transfer
After one byte or word has been transferred in response to one transfer request, the bus is released.
While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated.