Datasheet

Section 8 EXDMA Controller (EXDMAC)
Page 446 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
EXDMA
read
EXDMA
write
Address bus
φ
EDREQ
Idle Write
Bus release
Transfer
destination
EXDMA control
Channel
WriteIdle
Transfer source
Transfer
destination
Transfer source
Request Request
Minimum 3 cycles
Acceptance
resumed
Acceptance
resumed
Read
Bus release
EXDMA
read
EXDMA
write Bus release
One block transfer
One block transfer
Idle
[1] [4] [5] [6] [7][3][2]
[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] EXDMA cycle start; EDREQ pin high level sampling is started at rise of φ.
[4], [7] When EDREQ pin high level has been sampled, acceptance is resumed after completion of dead cycle.
(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)
Read
Request clearance period Request clearance period
Minimum 3 cycles
Figure 8.19 Example of Block Transfer Mode Transfer Activated
by EDREQ Pin Falling Edge
EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ
pin high level sampling is completed by the end of the EXDMA write cycle, acceptance resumes
after the end of the write cycle, and EDREQ pin low level sampling is performed again; this
sequence of operations is repeated until the end of the transfer.