Datasheet

Section 8 EXDMA Controller (EXDMAC)
R01UH0310EJ0500 Rev. 5.00 Page 441 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
The selected channel begins transfer after the currently transferring channel releases the bus. If
there is a bus request from a bus master other than the EXDMAC at this time, a cycle for the other
bus master is initiated. If there is no other bus request, the bus is released for one cycle.
Figure 8.14 shows examples of transfer timing in cases that include auto request cycle steal mode.
Channel 2 Channel 2 Channel 2 Channel 3 Channel 3
Bus
Conditions (1)
Channel 2: Auto request, cycle steal mode
Channel 3: External request, cycle steal mode, low level activation
Channel 2
EDA bit
Channel 3/
EDREQ3 pin
Channel 3 Channel 3 Channel 2 Channel 2Channel 3
Channel 2
Bus
Conditions (2)
Channel 2: External request, cycle steal mode, low level activation
Channel 3: Auto request, cycle steal mode
Channel 2/
EDREQ2 pin
Channel 2
EDA bit
Channel 3 Channel 3 Channel 2 Channel 3
Channel 2
Bus
Conditions (3)
Channel 2: Auto request, cycle steal mode
Channel 3: Auto request, cycle steal mode
*
: Bus release
Channel 2
EDA bit
Channel 3
EDA bit
*
*
**** *
*** *
** * *
Figure 8.14 Examples of Channel Priority Timing