Datasheet

Section 8 EXDMA Controller (EXDMAC)
R01UH0310EJ0500 Rev. 5.00 Page 425 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Figure 8.3 shows the data flow in single address mode, and figure 8.4 shows an example of the
timing.
Microcomputer
Data flow
External
address bus
External
data bus
EXDMAC
EDACK
EDREQ
External
memory
External device
with DACK
Figure 8.3 Data Flow in Single Address Mode