Datasheet

Section 8 EXDMA Controller (EXDMAC)
Page 414 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Bit Bit Name Initial Value R/W Description
14 BEF 0 R/(W)* Block Transfer Error Flag
Flag that indicates the occurrence of an error during
block transfer. If an NMI interrupt is generated
during block transfer, the EXDMAC immediately
terminates the EXDMA operation and sets this bit to
1. The address registers indicate the next transfer
addresses, but the data for which transfer has been
performed within the block size is lost.
0: No block transfer error
[Clearing condition]
Writing 0 to BEF after reading BEF = 1
1: Block transfer error
[Setting condition]
NMI interrupt during block transfer
13 EDRAKE 0 R/W EDRAK Pin Output Enable
Enables output from the EDREQ
acknowledge/transfer processing start (EDRAK) pin.
0: EDRAK pin output disabled
1: EDRAK pin output enabled
12 ETENDE 0 R/W ETEND Pin Output Enable
Enables output from the EXDMA transfer end
(ETEND) pin.
0: ETEND pin output disabled
1: ETEND pin output enabled
11 EDREQS 0 R/W EDREQ Select
Specifies low level sensing or falling edge sensing
as the sampling method for the EDREQ pin used in
external request mode.
0: Low level sensing (Low level sensing is used for
the first transfer after transfer is enabled.)
1: Falling edge sensing