Datasheet

Section 7 DMA Controller (DMAC)
R01UH0310EJ0500 Rev. 5.00 Page 395 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
DMA read DMA write DMA read DMA write DMA read DMA write
DMA
read
Address bus
φ
RD
HWR
LWR
DMA control
Channel 0A
Channel 0B
Channel 1
Idle Write
Idle Read Write Idle Read Write Read
Request
hold
Request
hold
Bus
release
Channel 0A
transfer
Bus
release
Channel 0B
transfer
Channel 1 transfer
Bus
release
Request
hold
Read
Selection
Non-
selection
Selection
Request clear
Request clear
Request clear
Figure 7.34 Example of Multi-Channel Transfer