Datasheet

Section 7 DMA Controller (DMAC)
Page 388 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
(3) DREQ Pin Falling Edge Activation Timing
Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected.
Figure 7.30 shows an example of single address mode transfer activated by the DREQ pin falling
edge.
DREQ
Bus release DMA single DMA single
Address bus
φ
DMA control
Channel
[2]
DACK
Transfer source/
destination
Idle Idle Idle
[1] [3] [5][4] [6] [7]
Acceptance resumesAcceptance resumes
Bus release Bus release
Transfer source/
destination
Request Request
Request clear
period
Request clear
period
Minimum of
2 cycles
Minimum of
2 cycles
SingleSingle
[1] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts.
[4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the single
cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and
the request is held.)
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.30 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer