Datasheet

Section 7 DMA Controller (DMAC)
Page 330 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Bit Bit Name Initial Value R/W Description
3
2
1
0
DTF3
DTF2
DTF1
DTF0
0
0
0
0
R/W
R/W
R/W
R/W
• Block Transfer Mode
0000: Setting prohibited
0001: Activated by A/D converter conversion end
interrupt
0010: Activated by DREQ pin falling edge input
(detected as a low level in the first transfer
after transfer is enabled)
0011: Activated by DREQ pin low-level input
0100: Activated by SCI channel 0 transmit data
empty interrupt
0101: Activated by SCI channel 0 receive data full
interrupt
0110: Activated by SCI channel 1 transmit data
empty interrupt
0111: Activated by SCI channel 1 receive data full
interrupt
1000: Activated by TPU channel 0 compare
match/input capture A interrupt
1001: Activated by TPU channel 1 compare
match/input capture A interrupt
1010: Activated by TPU channel 2 compare
match/input capture A interrupt
1011: Activated by TPU channel 3 compare
match/input capture A interrupt
1100: Activated by TPU channel 4 compare
match/input capture A interrupt
1101: Activated by TPU channel 5 compare
match/input capture A interrupt
1110: Setting prohibited
1111: Setting prohibited
The same factor can be selected for more than
one channel. In this case, activation starts with the
highest-priority channel according to the relative
channel priorities. For relative channel priorities,
see section 7.5.12, Multi-Channel Operation.
[Legend]
x: Don't care