Datasheet

Section 6 Bus Controller (BSC)
R01UH0310EJ0500 Rev. 5.00 Page 313 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
6.15.4 BREQO Output Timing
When the BREQOE bit is set to 1 and the BREQO signal is output, BREQO may go low before
the BACK signal.
This will occur if the next external access request or CBR refresh request occurs while internal bus
arbitration is in progress after the chip samples a low level of BREQ.
Note: The CBR refreshing control is not supported by the 5-V version.
6.15.5 Notes on Usage of the Synchronous DRAM
(1) Connection Clock
Be sure to set the clock to be connected to the synchronous DRAM to SDRAMφ.
(2) WAIT Pin
In the continuous synchronous DRAM space, insertion of the wait state by the WAIT pin is
disabled regardless of the setting of the WAITE bit in BCR.
(3) Bank Control
This LSI cannot carry out the bank control of the synchronous DRAM. All banks are selected.
(4) Burst Access
The burst read/burst write mode of the synchronous DRAM is not supported. When setting the
mode register of the synchronous DRAM, set to the burst read/single write and set the burst length
to 1.
(5) CAS Latency
When connecting a synchronous DRAM having CAS latency of 1, set the BE bit to 0 in the
DRAMCR.
Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424
Group.