Datasheet

Section 6 Bus Controller (BSC)
R01UH0310EJ0500 Rev. 5.00 Page 301 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Setting the DRMI bit in DRACCR to 1 enables an idle cycle to be inserted in the case of
consecutive read and write operations in DRAM/continuous synchronous DRAM space burst
access. Figures 6.93 and 6.94 show an example of the timing for idle cycle insertion in the case of
consecutive read and write accesses to DRAM/continuous synchronous DRAM space.
T
p
Address bus
Idle cycle
Data bus
T
r
T
c1
T
c2
DRAM space writeDRAM space read
T
c2
T
i
T
c1
RASn (CSn)
UCAS, LCAS
WE (HWR)
OE (RD)
Note: n = 2 to 5
φ
Figure 6.93 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and
Write Accesses to DRAM Space in RAS Down Mode