Datasheet

Section 6 Bus Controller (BSC)
Page 300 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Previous Access Next Access ICIS2 ICIS1 ICIS0 DRMI IDLC Idle cycle
0 ⎯ ⎯ ⎯ ⎯ Disabled
1 ⎯ ⎯ ⎯ 0 1 state inserted
Normal space read
1 2 states inserted
0 ⎯ ⎯ ⎯ ⎯ Disabled
1 ⎯ ⎯ ⎯ 0 1 state inserted
Normal space write
DRAM*
1
/continuous
synchronous DRAM*
2
space read
1 2 states inserted
0 ⎯ ⎯ ⎯ ⎯ Disabled
1 ⎯ ⎯ ⎯ 0 1 state inserted
Normal space read
1 2 states inserted
0 ⎯ ⎯ ⎯ ⎯ Disabled
1 ⎯ ⎯ ⎯ 0 1 state inserted
DRAM*
1
/continuous
synchronous
DRAM*
2
space write
DRAM*
1
/continuous
synchronous DRAM*
2
space read
1 2 states inserted
Notes: 1. The DRAM interface is not supported by the 5-V version.
2. Not supported by the H8S/2426 Group and H8S/2424 Group.