Datasheet

Section 6 Bus Controller (BSC)
Page 296 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
(b) Normal space access after DRAM space write access
While the ICIS2 bit is set to 1 in BCR and a normal space read access occurs after DRAM space
write access, idle cycle is inserted in the first read cycle. The number of states of the idle cycle to
be inserted is in accordance with the setting of the IDLC bit. It does not depend on the DRMI bit
in DRACCR. Figure 6.90 shows an example of idle cycle operation when the ICIS2 bit is set to 1.
T
p
Address bus
φ
RD
RAS
HWR, LWR
U
CAS, LCAS
External space read
Idle cycle
Data bus
T
r
T
c1
T
c2
T
1
DRAM space readDRAM space read
T
2
T
c2
T
3
T
i
T
c1
Figure 6.90 Example of Idle Cycle Operation after DRAM Write Access
(IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0)
(8) Idle Cycle in Case of Normal Space Access after Continuous Synchronous DRAM
Space Access:
Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424
Group.