Datasheet

Section 6 Bus Controller (BSC)
R01UH0310EJ0500 Rev. 5.00 Page 291 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid
and an idle cycle is inserted. However, in read access, note that the timings of DQMU and DQML
differ according to the settings of the IDLC bit. The timing in this case is illustrated in figures 6.85
and 6.86. In write access, DQMU and DQML are not in accordance with the settings of the IDLC
bit. The timing in this case is illustrated in figure 6.87.
T
p
Address bus External addressColumn address 1 Column address 2
External address
Row
address
Column
address
Idle cycle
Data bus
T
r
T
c1
T
cl
T
c2
T
3
T
c1
Continuous synchronous
DRAM space read External space read
Continuous synchronous
DRAM space read
T
2
T
i
T
1
RAS
CAS
WE
RD
HWR, LWR
CKE
High
High
PALL ACTV READ
NOP NOPREAD
DQMU, DQML
T
Cl
T
c2
Precharge-sel
φ
Row
address
Figure 6.85 Example of Idle Cycle Operation in RAS Down Mode
(Read in Different Area) (IDLC = 0, CAS Latency 2)