Datasheet

Section 6 Bus Controller (BSC)
Page 288 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
(5) Idle Cycle in Case of DRAM Space Access after Normal Space Access
In a DRAM space access following a normal space access, the settings of bits ICIS2, ICIS1,
ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads in different areas,
for example, if the second read is a full access to DRAM space, only a T
p
cycle is inserted, and a
T
i
cycle is not. The timing in this case is shown in figure 6.81.
Note: The DRAM interface is not supported by the 5-V version.
T
1
A
ddress bus
φ
RD
External read
Data bus
T
2
T
3
T
p
T
r
DRAM space read
T
c1
T
c2
Figure 6.81 Example of DRAM Full Access after External Read
(CAST = 0)
In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid
and an idle cycle is inserted. The timing in this case is illustrated in figures 6.82 and 6.83.