Datasheet

Section 6 Bus Controller (BSC)
R01UH0310EJ0500 Rev. 5.00 Page 271 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
T
Rp1
φ
SDRAMφ
RAS
CAS
WE
CKE
PALL NOP REF NOP
Address bus
T
Rp2
T
Rrw
T
Rr
T
Rc1
T
Rc2
Precharge-sel
High
Figure 6.67 Auto Refresh Timing
(TPC = 1, TPC0 = 1, RCW1 = 0, RCW0 = 1)
When the interval specification from the REF command to the ACTV cannot be satisfied, setting
the RLW1 and RLW0 bits of REFCR enables one to three wait states to be inserted in the refresh
cycle. Set the optimum number of waits according to the synchronous DRAM connected and the
operating frequency of this LSI. Figure 6.68 shows the timing when one wait state is inserted.