Datasheet

Section 6 Bus Controller (BSC)
Page 266 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
T
p
SDRAM φ
φ
RAS
Read
CAS
WE
CKE
PALL ACTV READ READNOP NOP
DQMU, DQML
Data bus
Address bus
T
r
T
c1
T
cl
T
c2
T
c1
T
cl
T
c2
Row address
Column
address 1
Column address Column address 2
Precharge-sel
Row address
High
RAS
Write
CAS
WE
CKE
PALL ACTV NOP NOP NOPWRIT WRIT
DQMU, DQML
Data bus
High
Figure 6.64 Operation Timing of Burst Access
(BE = 1, SDWCD = 0, CAS Latency 2)