Datasheet

Section 6 Bus Controller (BSC)
R01UH0310EJ0500 Rev. 5.00 Page 263 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
T
p
SDRAMφ
φ
RAS
CAS
WE
CKE
PALL ACTV READ NOP
DQMU
DQML
Lower data bus
Upper data bus
Address bus
T
r
T
c1
T
cl
T
c2
Row address Column address Column address
Precharge-sel
Row address
High
High
High impedance
Figure 6.62 DQMU and DQML Control Timing
(Lower Byte Read Access: CAS Latency 2)