Datasheet

Section 6 Bus Controller (BSC)
R01UH0310EJ0500 Rev. 5.00 Page 261 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
6.8.10 Bus Cycle Control in Write Cycle
By setting the SDWCD bit of the DRACCR to 1, the CAS latency control cycle (Tc1) that is
inserted by the WTCRB register in the write access of the synchronous DRAM can be disabled.
Disabling the CAS latency control cycle can reduce the write-access cycle count as compared to
synchronous DRAM read access. Figure 6.60 shows the write access timing when the CAS
latency control cycle is disabled.
T
p
SDRAMφ
RAS
CAS
WE
CKE
PALL ACTV WRITNOP
DQMU, DQML
Data bus
Address bus
φ
T
r
T
c1
T
c2
Row address Column address Column address
Precharge-sel
Row address
High
Figure 6.60 Example of Write Access Timing when CAS Latency Control Cycle Is Disabled
(SDWCD = 1)