Datasheet

Section 6 Bus Controller (BSC)
R01UH0310EJ0500 Rev. 5.00 Page 249 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
(2) When DDS = 0 or EDDS = 0
When DRAM space is accessed in DMAC or EXDMAC single address transfer mode, full access
(normal access) is always performed. With the DRAM interface, the DACK or EDACK output
goes low from the T
r
state.
In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used
when accessing DRAM space.
Figure 6.54 shows the DACK or EDACK output timing for the DRAM interface when DDS = 0 or
EDDS = 0.
T
p
RASn (CSn)
Read
Write
UCAS, LCAS
WE (HWR)
OE (RD)
Data bus
WE (HWR)
OE (RD)
Data bus
DACK or EDACK
Address bus
φ
T
r
T
c1
T
c2
Note: n = 2 to 5
T
c3
Row address Column address
High
High
Figure 6.54 Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0
(RAST = 0, CAST = 1)