Datasheet

Section 6 Bus Controller (BSC)
Page 246 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
In some DRAMs provided with a self-refresh mode, the RAS signal precharge time immediately
after self-refreshing is longer than the normal precharge time. A setting can be made in bits
TPCS2 to TPCS0 in REFCR to make the precharge time immediately after self-refreshing from 1
to 7 states longer than the normal precharge time. In this case, too, normal precharging is
performed according to the setting of bits TPC1 and TPC0 in DRACCR, and therefore a setting
should be made to give the optimum post-self-refresh precharge time, including this time. Figure
6.52 shows an example of the timing when the precharge time immediately after self-refreshing is
extended by 2 states.
DRAM space write
TR
c3
TR
p1
TR
p2
T
p
T
r
Software
standby
T
c1
T
c2
Note: n = 2 to 5
RASn (CSn)
UCAS, LCAS
OE (RD)
WE (HWR)
Data bus
Address bus
φ
Figure 6.52 Example of Timing when Precharge Time after Self-Refreshing Is Extended
by 2 States