Datasheet

Section 6 Bus Controller (BSC)
R01UH0310EJ0500 Rev. 5.00 Page 245 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
(2) Self-Refreshing
A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In
this mode, refresh timing and refresh addresses are generated within the DRAM.
To select self-refreshing, set the RFSHE bit and SLFRF bit to 1 in REFCR. When a SLEEP
instruction is executed to enter software standby mode, the CAS and RAS signals are output and
DRAM enters self-refresh mode, as shown in figure 6.51.
When software standby mode is exited, the SLFRF bit is cleared to 0 and self-refresh mode is
exited automatically. If a CBR refresh request occurs when making a transition to software
standby mode, CBR refreshing is executed, and then self-refresh mode is entered.
When using self-refresh mode, the OPE bit must not be cleared to 0 in the SBYCR register.
T
Rp
T
Rr
UCAS, LCAS
Software
standby
T
Rc3
HWR (WE)
CSn (RASn)
φ
Note: n = 2 to 5
High
Figure 6.51 Self-Refresh Timing