Datasheet
Section 6 Bus Controller (BSC)
R01UH0310EJ0500 Rev. 5.00 Page 243 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
A setting can be made in bits RCW1 and RCW0 in REFCR to delay RAS signal output by one to
three cycles. Use bits RLW1 and RLW0 in REFCR to adjust the width of the RAS signal. The
settings of bits RCW1, RCW0, RLW1, and RLW0 are valid only in refresh operations.
Figure 6.49 shows the timing when bits RCW1 and RCW0 are set.
T
Rp
CSn (RASn)
T
Rrw
T
Rr
T
Rc1
UCAS, CAS
T
Rc2
φ
Figure 6.49 CBR Refresh Timing
(RCW1 = 0, RCW0 = 1, RLW1 = 0, RLW0 = 0)