Datasheet

Section 6 Bus Controller (BSC)
Page 240 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
• RAS Up Mode
To select RAS up mode, clear the RCDM bit to 0 in DRAMCR. Each time access to DRAM
space is interrupted and another space is accessed, the RAS signal goes high again. Burst
operation is only performed if DRAM space is continuous. Figure 6.45 shows an example of
the timing in RAS up mode.
Normal space
read
DRAM space
read
T
p
T
r
T
c1
T
c2
T
c1
T
c2
DRAM space read
T
1
T
2
Note: n = 2 to 5
RASn (CSn)
UCAS, LCAS
RD
OE
Data bus
A
ddress bus
φ
Row address Column address 1 Column address 2 External address
Figure 6.45 Example of Operation Timing in RAS Up Mode
(RAST = 0, CAST = 0)