Datasheet

Section 6 Bus Controller (BSC)
Page 232 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
By program wait
T
p
Address bus
φ
WAIT
T
r
T
c1
T
w
T
w
T
c2
By WAIT pin
RASn (CSn)
Read
Write
UCAS, LCAS
UCAS, LCAS
WE (HWR)
OE (RD)
Data bus
WE (HWR)
OE (RD)
Data bus
Row address Column address
High
High
Note: Downward arrows indicate the timing of WAIT pin sampling.
n = 2 to 5
Figure 6.38 Example of Wait State Insertion Timing
(2-State Column Address Output)