Datasheet

Section 6 Bus Controller (BSC)
Page 216 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
AD15 to AD8
AD7 to AD0
AD15 to AD8
AD7 to AD0
HWR
LWR
CSn
AH
RD
Tma1 T1 T2 T3Tma2
Address cycle Data cycle
φ
Address bus
Write
Read
Address
Address
Read
data
Write data
Notes: 1. n = 6, 7
2. When RDNn = 1
Address
Address
Figure 6.27 Bus Timing for 16-Bit, 3-State Data Access Space
(Odd Address Byte Access)