Datasheet

Section 6 Bus Controller (BSC)
Page 210 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Address cycle Data cycle
Tma1 Tma2 T1 T2
φ
Address bus
CSn
AH
RD
HWR
LWR
AD15 to AD8
AD15 to AD8
Write
Read
Address
Address
Read
data
Write data
Notes: 1. n = 6, 7
2. When RDNn = 0
Figure 6.21 Bus Timing for 8-Bit, 2-State Data Access Space